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STM32L4 数据表(PDF) 2 Page - STMicroelectronics

部件名 STM32L4
功能描述  This module presentation presents the key differences between the STM32L4 and the STM32L476/L486 devices.
PDF  33 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STM32L4 数据表(HTML) 2 Page - STMicroelectronics

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STM32L4Rxxx/Sxxx and
STM32L4P5xx/Q5xx Block Diagram
• Up to 120MHz, 406 CoreMark
• Up to 2MB Flash / 640KB SRAM for
STM32L4Rxxx/Sxxx devices
• Up to 1MB Flash / 320KB SRAM for
STM32L4P5xx/Q5xx devices
• MIPI-DSI 2 Lanes
• LCD-TFT controller
• Chrom-ART
• Chrom-GRC
• 2xOctoSPI
2
USB OTG, 1x CAN,
2x SD/SDIO/MMC(2), 3x SPI,
4x I²C, 2xOctoSPI,
5x USART + 1x ULP UART
Connectivity
Cortex-M4
120 MHz
FPU
MPU
ETM
Up to
2-Mbyte Flash
with ECC
Dual Bank
Up to 640-Kbyte
RAM
2xDMA
ART
Accelerator™
AES (256-bit), SHA 256,
PKA (3),TRNG, 2x SAI,
DFSDM (8 channels)
Digital
2x 12-bit ADC(4), 2x DAC,
2x comparators, 2x op amps
1x temperature sensor
Analog
FSMC 8-/16-bit
(TFT-LCD, SRAM, NOR,
NAND)
Parallel Interface
MIPI-DSI(1) 2 Lanes 500Mps
LCD-TFT Controller
Display
17 timers including:
2 x 16-bit advanced motor
control timers
2 x ULP timers
7 x 16-bit-timers
2 x 32-bit timers
Timers
I/Os
Up to 114 I/Os
Touch-sensing controller
Camera Interface
Chrom-ART ™
Chrom-GRC ™(1)
(1)
MIPI-DSI and Chrom-GRC are available only on STM32L4Rxxx/Sxxx devices
(2)
2x SDMMC for STM32L4P5xx/Q5xx devices and 1x SDMMC for STM32L4Rxxx/Sxxx devices
(3)
PKA only for STM32L4P5xx/Q5xx devices
(4)
2x ADC for STM32L4P5xx/Q5xx devices and 1x ADC for STM32L4Rxxx/Sxxx devices
The STM32L4+ series stretches the STM32L4 technology
by offering higher performance, that is to say 120 MHz/406
CoreMark executing from internal Flash memory
The new STM32L4+ embeds up to 2 Mbytes of dual-bank
Flash memory and up to 640 Kbytes of embedded SRAM.
It also embeds advanced graphic features enabling state-
of-the-art Graphic User Interfaces.:
•
The Chrom-ART Accelerator™, the ST proprietary 2D
hardware graphic accelerator, efficiently handles
repetitive graphic operations releasing the main CPU
capabilities for real-time processing or even more
2



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