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MPFS250T 数据表(PDF) 1 Page - Microchip Technology |
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MPFS250T 数据表(HTML) 1 Page - Microchip Technology |
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1 / 50 page  PolarFire® SoC Product Overview Overview PolarFire® SoC is built upon the award-winning PolarFire FPGA non-volatile FPGA platform. Featuring a five core Linux capable processor subsystem based on the RISC-V ISA, PolarFire SoC brings to market an innovative, mid- range, embedded compute platform that inherits all the benefits of the PolarFire FPGA product family. The RISC-V CPU micro-architecture implementation is a simple, 5-stage single issue in order pipeline that does not suffer from the Meltdown and Spectre exploits found in common out-of-order machines. All five CPU cores are coherent with the memory subsystem allowing a versatile mix of deterministic real time systems and Linux in a single, multi-core CPU cluster. With Secure Boot built-in, innovative Linux and Real Time modes, a large Flexible L2 memory subsystem, and a rich set of embedded peripherals, PolarFire SoC provides designers new choices in secure, power-efficient, embedded compute platforms. This document describes the features of PolarFire SoC extended commercial (0 °C to 100 °C Tj) and industrial (–40 °C to 100 °C Tj) device offerings. Microprocessor Subsystem Features • 64-bit RV64GC (RV64GC or RV64IMAFDC: RISC-V 64-bit Integer, Multiply and divide, Atomic, Floating point single and Double precision and Compressed instruction set support) quad application processing cores, FMAX of 667 MHz (–40 °C to 100 °C Tj), 3.125 CoreMarks/MHz, 1.714 DMIPS/MHz – L1 memory subsystem with single-error correct, double-error detect (SECDED) • 32 KB 8-way instruction cache or optional 28 Kbyes tightly integrated memory • 32 KB 8-way data cache • Memory Management Unit (MMU) • Physical Memory Protection (PMP) unit • 64-bit RV64IMAC (RV64IMAC: RISC-V 64-bit Integer, Multiply and divide, Atomic, and Compressed instruction set support) monitor processor core, FMAX of 667 MHz (–40 °C to 100 °C Tj), 3.125 CoreMarks/MHz, 1.714 DMIPS/MHz – L1 memory subsystem with SECDED • 16 KB 2-way instruction cache – 8 KB scratch pad memory – PMP unit • Flexible 2 MB L2 memory subsystem with SECDED configurable as: – 16-way set associative L2 cache with write-back policy – Loosely Integrated Memory (LIM) mode for deterministic access – Coherent directly addressable Scratchpad Memory mode for shared messages across cores • Integrated 36-bit DDR4/DDR3/LPDDR4/LPDDR3 memory controller with SECDED – DDR4 at 1.6 Gbps with a 8 GB address reach • Cache coherent CPU bus matrix • AMBA I/O switch with QoS and Memory Protection Unit (MPU) • Integrated 128 KB embedded non-volatile memory (eNVM) for boot code • Boot options – Microchip secure boot – User defined, PUF-protected secure boot © 2021 Microchip Technology Inc. and its subsidiaries Overview DS60001656C-page 1 |
类似零件编号 - MPFS250T |
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类似说明 - MPFS250T |
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