MPFS250TLS datasheet(68/128 Pages) MICROCHIP

68 / 128 page

10. Period jitter is measured at the output of the device using HSUL12 output buffers and includes the jitter

effects of the reference clock source, PLL, clock routing networks, and output buffer. PLL is configured

with internal feedback enabled and in integer mode. FPGA fabric is active during testing (75% utilization).

Note: In order to meet all datasheet specifications, the PLL must be programmed such that the PLL Loop

Bandwidth < (0.0017 * VCO Frequency) – 0.4863 MHz. The Libero PLL configuration tool will enforce this

rule when creating PLL configurations.

6.3.3

DLL

The following table provides information about DLL.

Table 75 • DLL Electrical Characteristics

Unit

Max

Typ

Min

Symbol

Parameter

MHz

800

133

FINF

Input reference

clock frequency

MHz

800

133

FINFDBF

Input feedback

clock frequency

MHz

800

133

FOUTPF

Primary output

clock frequency

MHz

800

33.3

FOUTSF

Secondary output

clock frequency

200

FINJ

Input clock cycle-

to-cycle jitter

Max (250 ps, 15%

of clock period)

TOUTJITTERCC

Output clock cycle-

to-cycle jitter (with

clean input clock)

Max (300 ps, 20%

of clock period)

TOUTJITTERP

Output clock period

jitter (with clean in-

put clock)

±150

TSKEW

Output clock-to-

clock skew be-

tween two outputs

with the same

phase settings

Reference clock cy-

cles

16K

TLOCK

DLL lock time

TMRPW

Minimum reset

pulse width

TMIPW

Minimum input

pulse width

400

TMPWH

Minimum input

clock pulse width

high

400

TMPWL

Minimum input

clock pulse width

low

Microsemi Proprietary and Confidential. DS0147 Revision 1.0

AC Switching Characteristics

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