CC2430-RTR1-F128 datasheet(160/234 Pages) TI

160 / 234 page

CC2430

CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A

Page 160 of 232

Note: if flash erase operations are

performed from within flash memory and

the watchdog timer is enabled, a watchdog

timer interval must be selected that is

longer than 20 ms, the duration of the

flash erase operation, so that the CPU will

manage to clear the watchdog timer.

Performing flash erase from flash memory.

The steps required to perform a flash page

erase from within flash memory are

outlined in Figure 36.

Note that, while executing program code

from within flash memory, when a flash

erase or write operation is initiated,

program execution will resume from the

next instruction when the flash controller

has completed the operation.

; Erase page in flash memory

; Assumes 32 MHz system clock is used

;

CLR

;mask interrupts

C1:

MOV

A,FCTL

;wait until flash controller is ready

ACC.7,C1

MOV

FADDRH,#00h

;setup flash address high

MOV

FWT,#2Ah

;setup flash timing

MOV

FCTL,#01h

;erase page

RET

;continues here when flash is ready

Figure 36: Flash page erase performed from flash memory

13.14.3 Flash Lock Protection

For software protection purposes a set of

lock protection bits can be written once

after each chip erase has been performed.

The lock protect bits can only be written

through the Debug Interface. There are

three kinds of lock protect bits as

described in this section. The flash lock

bits reside at location 0x000 in the Flash

Information page as described in section

12.11.

The LSIZE[2:0] lock protect bits are

used to define a section of the flash

memory which is write protected. The size

of the write protected area can be set by

the LSIZE[2:0] lock protect bits in sizes

of eight steps from 0 to 128 KB.

The second type of lock protect bits is

BBLOCK, which is used to lock the boot

sector page (page 0 ranging from address

0 to 0x07FF). When BBLOCK is set to 0,

the boot sector page is locked.

The third type of lock protect bit is

DBGLOCK, which is used to disable

hardware debug support through the

Debug Interface. When DBGLOCK is set to

0, all debug commands are disabled.

The lock protect bits are written as a

normal flash write to FWDATA, but the

Debug Interface needs to select the Flash

Information Page first instead of the Flash

Main Page which is the default setting.

The Information Page is selected through

the Debug Configuration which is written

through the Debug Interface only. Refer to

section 12.9 on page 62 for details on how

the Flash Information Page is selected

using the Debug Interface.

Table 40 defines the byte containing the

flash lock protection bits. Note that this is

not an SFR register, but instead the byte

stored

location

0x000

Flash

Information Page.

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