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CC2430-RTR1-F128 数据表(PDF) 162 Page - Texas Instruments

部件名 CC2430-RTR1-F128
功能描述  A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM
PDF  234 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

CC2430-RTR1-F128 数据表(HTML) 162 Page - Texas Instruments

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CC2430
CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A
Page 162 of 232
13.14.6 Flash Controller Registers
The
Flash
Controller
registers
are
described in this section.
FCTL (0xAE) – Flash Control
Bit
Name
Reset
R/W
Description
7
BUSY
0
R
Indicates that write or erase is in operation
6
SWBSY
0
R
Indicates that single write is busy; avoid writing to FWDATA
register while this is true
5
-
0
R/W
Not used.
4
CONTRD
0
R/W
Continuous read enable mode
0
Avoid wasting power; turn on read enables to flash only
when needed
1
Enable continuous read enables to flash when read is to
be done. Reduces internal switching of read enables, but
greatly increases power consumption.
3:2
0
R/W
Not used.
1
WRITE
0
R0/W
Page Write. Start writing page given by
FADDRH:FADDRL. If
ERASE is set to 1, a page erase is performed before the write.
0
ERASE
0
R0/W
Page Erase. Erase page that is given by
FADDRH[6:1]
FWDATA (0xAF) – Flash Write Data
Bit
Name
Reset
R/W
Description
7:0
FWDATA[7:0]
0x00
R/W
Flash write data. Data written to
FWDATA is written to flash when
FCTL.WRITE is set to 1.
FADDRH (0xAD) – Flash Address High Byte
Bit
Name
Reset
R/W
Description
7
-
0
R/W
Not used
6:0
FADDRH[6:0]
0x00
R/W
High byte of flash address
Bits 6:1 will select page to access, while bit 0 is MSB of row
access.
FADDRL (0xAC) – Flash Address Low Byte
Bit
Name
Reset
R/W
Description
7:0
FADDRL[7:0]
0x00
R/W
Low byte of flash address
Bit 0 of FADDRH and bits 7:6 will select which row to write to,
while bits 5:0 will select which location to write to.



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