HT36F2 datasheet(11/36 Pages) HOLTEK

11 / 36 page

HT36F2

Rev. 1.00

August 15, 2005

Power Down Operation

- HALT

The HALT mode is initialized by a

²HALT² instruction

and results in the following...

· The system oscillator will turn off but the WDT oscilla-

tor keeps running (If the WDT oscillator is selected).

Watchdog Timer

- WDT

· The contents of the on-chip RAM and registers remain

unchanged

· The WDT and WDT prescaler will be cleared and

starts to count again (if the clock comes from the WDT

oscillator).

· All I/O ports maintain their original status.

· The PDF flag is set and the TO flag is cleared.

· The HALT pin will output a high level signal to disable

the external ROM.

The system can leave the HALT mode by means of an

external reset, an interrupt, an external falling edge sig-

nal on port A or a WDT overflow. An external reset

causes a device initialization and the WDT overflow per-

forms a

²warm reset². By examining the TO and PDF

flags, the cause for a chip reset can be determined. The

PDF flag is cleared when there is a system power-up or by

executing the

²CLR WDT² instruction and it is set when a

²HALT² instruction is executed. The TO flag is set if the

WDT time-out occurs, and causes a wake-up that only re-

sets the Program Counter and SP, the others remain in

their original status.

The port A wake-up and interrupt methods can be con-

sidered as a continuation of normal execution. Each bit

in port A can be independently selected to wake-up the

device by mask option. Awakening from an I/O port stim-

ulus, the program will resume execution of the next in-

struction. If awakening from an interrupt, two sequences

may occur. If the related interrupts is disabled or the in-

terrupts is enabled but the stack is full, the program will

resume execution at the next instruction. If the interrupt

is enabled and the stack is not full, a regular interrupt re-

sponse takes place.

Once a wake-up event occurs, it takes 1024 tSYS (sys-

tem clock period) to resume to normal operation. In

other words, a dummy cycle period will be inserted after

the wake-up. If the wake-up results from an interrupt ac-

knowledge, the actual interrupt subroutine will be de-

layed by one more cycle. If the wake-up results in next

instruction execution, this will execute immediately after

a dummy period has finished. If an interrupt request flag

is set to

²1² before entering the HALT mode, the

wake-up function of the related interrupt will be disabled.

To minimize power consumption, all I/O pins should be

carefully managed before entering the HALT status.

Reset

There are 3 ways in which a reset can occur:

· RES reset during normal operation

· RES reset during HALT

· WDT time-out reset during normal operation

The WDT time-out during HALT is different from other

chip reset conditions, since it can perform a

²warm re -

set

² that just resets the Program Counter and SP, leav-

ing the other circuits to maintain their state. Some regis-

ters remain unchanged during any other reset

conditions. Most registers are reset to the

²initial condi-

tion

² when the reset conditions are met. By examining

the PDF and TO flags, the program can distinguish be-

tween different

²chip resets².

PDF

RESET Conditions

RES reset during power-up

RES reset during normal operation

RES wake-up HALT

WDT time-out during normal operation

WDT wake-up HALT

Note:

²u² stands for ²unchanged²

To guarantee that the system oscillator has started and

stabilized, the SST (System Start-up Timer) provides an

extra-delay of 1024 system clock pulses during system

power up or when the system awakes from a HALT

state.

When a system power-up occurs, the SST delay is

added during the reset period. But when the reset co-

mes from the RES pin, the SST delay is disabled. Any

wake-up from HALT will enable the SST delay.

The functional units chip reset status are shown below.

Program Counter

000H

Interrupt

Disable

Prescaler

Clear

WDT

Clear. After master reset,

WDT begins counting

Timer Counter (0/1)

Off

Input/output ports

Input mode

Stack Pointer

Points to the top of stack

t S S T

R E S

V D D

S S T T i m e - o u t

C h i p R e s e t

Reset Timing Chart

HT36F2 数据表(PDF) 11 Page - Holtek Semiconductor Inc

HT36F2 数据表(HTML) 11 Page - Holtek Semiconductor Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

数据表下载