Symbol

Parameters

Test conditions

Min.

Typ.

Max.

Unit

AVCC = DVCC = +2.7 V to +3.6 V

IOZH, IOZL

High impedance output

leakage current

AVCC = DVCC = +2.7 V to +3.6 V

-1

+1

µA

COUT

High-impedance output

capacitance

4.5

pF

Power supply characteristics, CL=10 pF

IAVCC + IDVCC

Total supply current, normal

mode (/CS low)

AVCC = DVCC = +2.7 V to +3.6 V,

0.9

2

mA

Total supply

current,shutdown mode

(/CS high)

AVCC = DVCC = +2.7 V to +3.6 V,

0.11

10

µA

Clocking characteristics, AVCC = DVCC = +2.7 V to +3.6 V

Conversion (hold) time

13

SCLK

cycles

DC

SCLK duty cycle

40

60

%

Acquisition (track) time

cycles

See Section 4 Timing diagrams

3

SCLK

cycles

Throughput time

acquisition time +

conversion time

16

SCLK

cycles

Aperture delay

4

ns

Timing specifications, AVCC = DVCC = +2.7 V to +3.6 V

/CS hold time after SCLK

rising edge

10

0

ns

/CS setup time prior SCLK

rising edge

10

4.5

/CSfalling edge to DOUT

enabled

5

30

ns

DOUT access time after

SCLK falling edge

17

27

ns

DOUT hold time after SCLK

falling edge

7

4

ns

DIN set-up time prior to

SCLK rising edge

10

ns

DIN hold time after SCLK

rising edge

10

ns

Min. SCLK high time

ns

Min. SCLK low time

ns

/CS rising edge to DOUT

high-impedance

DOUT falling

2.4

20

ns

DOUT rising

0.9

20

ns

1. Limits are guaranteed by functional test.

2. Clock may be in any state (high or low) when /CS goes high. Set-up and hold time restrictions apply only

to /CS going low.

LEOAD128

Electrical characteristics

DS13668 - Rev 2

page 6/20