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MM54HC74J 数据表(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部件名 MM54HC74J
功能描述  Dual D Flip-Flop with Preset and Clear
PDF  4 Pages
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制造商  NSC [National Semiconductor (TI)]
网页  http://www.national.com
标志 NSC - National Semiconductor (TI)

MM54HC74J 数据表(HTML) 3 Page - National Semiconductor (TI)

  MM54HC74J Datasheet HTML 1Page - National Semiconductor (TI) MM54HC74J Datasheet HTML 2Page - National Semiconductor (TI) MM54HC74J Datasheet HTML 3Page - National Semiconductor (TI) MM54HC74J Datasheet HTML 4Page - National Semiconductor (TI)  
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AC Electrical Characteristics VCCe5V TAe25 C CLe15 pF tretfe6ns
Symbol
Parameter
Conditions
Typ
Guaranteed
Units
Limit
fMAX
Maximum Operating
72
30
MHz
Frequency
tPHL tPLH
Maximum Propagation
10
30
ns
Delay Clock to Q or Q
tPHL tPLH
Maximum Propagation
17
40
ns
Delay Preset or Clear to Q or Q
tREM
Minimum Removal Time
6
5
ns
Preset or Clear to Clock
ts
Minimum Setup Time
10
20
ns
Data to Clock
tH
Minimum Hold Time
0
0
ns
Clock to Data
tW
Minimum Pulse Width
8
16
ns
Clock Preset or Clear
AC Electrical Characteristics CLe50 pF tretfe6 ns (unless otherwise specified)
TAe25 C
74HC
54HC
Symbol
Parameter
Conditions
VCC
TAeb40 to 85 CTAeb55 to 125 C
Units
Typ
Guaranteed Limits
fMAX
Maximum Operating
20V
22
6
5
4
MHz
Frequency
45V
72
30
24
20
MHz
60V
94
35
28
24
MHz
tPHL tPLH
Maximum Propagation
20V
34
110
140
165
ns
Delay Clock to Q or Q
45V
12
22
28
33
ns
60V
10
19
24
28
ns
tPHL tPLH
Maximum Propagation
20V
66
150
190
225
ns
Delay Preset or Clear
45V
20
30
38
45
ns
ToQorQ
60V
16
26
33
38
ns
tREM
Minimum Removal Time
20V
20
50
65
75
ns
Preset or Clear
45V
6
10
13
15
ns
To Clock
60V
5
9
11
13
ns
ts
Minimum Setup Time
20V
35
80
100
120
ns
Data to Clock
45V
10
16
20
24
ns
60V
8
14
17
20
ns
tH
Minimum Hold Time
20V
0
0
0
ns
Clock to Data
45V
0
0
0
ns
60V
0
0
0
ns
tW
Minimum Pulse Width
20V
30
80
101
119
ns
Clock Preset or Clear
45V
9
16
20
24
ns
60V
8
14
17
20
ns
tTLH tTHL
Maximum Output
20V
25
75
95
110
ns
Rise and Fall Time
45V
7
15
19
22
ns
60V
6
13
16
19
ns
tr tf
Maximum Input Rise and
20V
1000
1000
1000
ns
Fall Time
45V
500
500
500
ns
60V
400
400
400
ns
CPD
Power Dissipation
(per flip-flop)
80
pF
Capacitance (Note 5)
CIN
Maximum Input
5
10
10
10
pF
Capacitance
Note 5
CPD determines the no load dynamic power consumption PDeCPD VCC2 faICC VCC and the no load dynamic current consumption ISeCPD VCC faICC
3



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