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ASM330LHH 数据表(PDF) 19 Page - STMicroelectronics |
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ASM330LHH 数据表(HTML) 19 Page - STMicroelectronics |
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19 / 84 page  DocID031239 Rev 4 19/84 ASM330LHH Module specifications 84 4.4 Communication interface characteristics 4.4.1 SPI - serial peripheral interface Subject to general operating conditions for Vdd and Top. Figure 2. SPI slave timing diagram (in mode 3) Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output ports. Table 6. SPI slave timing values (in mode 3) Symbol Parameter Value(1) Unit Min Max tc(SPC) SPI clock cycle 100 ns fc(SPC) SPI clock frequency 10 MHz tsu(CS) CS setup time 5 ns th(CS) CS hold time 20 tsu(SI) SDI input setup time 5 th(SI) SDI input hold time 15 tv(SO) SDO valid output time 50 th(SO) SDO output hold time 5 tdis(SO) SDO output disable time 50 1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production |
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