Register description

LIS3DHH

22/29

DocID030220 Rev 3

7.3

INT1_CTRL (21h)

INT1 pin control register.

Table 12. INT1_CTRL register

Table 13. INT1_CTRL register description

7.4

INT2_CTRL (22h)

INT2 pin control register.

Table 14. INT2_CTRL register

Table 15. INT2_CTRL register description

INT1_

DRDY

INT1_

BOOT

INT1_

OVR

INT1_

FSS5

INT1_FTH INT1_ EXT

0(1)

1. These bits must be set to ‘0’ for the correct operation of the device.

0(1)

INT1_DRDY

Accelerometer data ready on INT1 pin. Default value: 0

(0: disabled; 1: enabled)

INT1_ BOOT

Boot status available on INT1 pin. Default value: 0

(0: disabled; 1: enabled)

INT1_OVR

Overrun flag on INT1 pin. Default value: 0

(0: disabled; 1: enabled)

INT1_ FSS5

FSS5 full FIFO flag on INT1 pin. Default value: 0

(0: disabled; 1: enabled)

INT1_FTH

FIFO threshold flag on INT1 pin. Default value: 0

(0: disabled; 1: enabled)

INT1_ EXT

INT1 pin configuration. Default value: 0

It configures the INT1 pad as output for FIFO flags or as external asynchronous

input trigger to FIFO.

INT2 pad is always available as output for FIFO flags.

(0: INT1 as output interrupt; 1: INT1 as input channel)

INT2_DRDY INT2_BOOT

INT2_OVR INT2_ FSS5 INT2_FTH

0(1)

1. These bits must be set to ‘0’ for the correct operation of the device.

0(1)

0(1)

INT2_DRDY

Accelerometer data ready on INT2 pin. Default value: 0

(0: disabled; 1: enabled)

INT2_ BOOT

Boot status available on INT2 pin. Default value: 0

(0: disabled; 1: enabled)

INT2_OVR

Overrun flag on INT2 pin. Default value: 0

(0: disabled; 1: enabled)

INT2_ FSS5

FSS5 full FIFO flag on INT2 pin. Default value: 0

(0: disabled; 1: enabled)

INT2_FTH

FIFO threshold flag on INT2 pin. Default value: 0

(0: disabled; 1: enabled)