TSC2010H datasheet(49/50 Pages) STMICROELECTRONICS

49 / 50 page

Figure 51.

ON/OFF delay for shutdown mode ..................................................... 23

Figure 52.

Output voltage vs. Vsense beyond the sense operating ........................................ 23

Figure 53.

Power-up time delay ............................................................... 23

Figure 54.

Power supply when Vicm > Vcc ........................................................ 24

Figure 55.

Input bias current vs. common mode voltage Vcc = 5 V ....................................... 25

Figure 56.

Power supply when Vicm < Gnd ....................................................... 25

Figure 57.

Vref powered by an external voltage source ............................................... 26

Figure 58.

Output reference to ground .......................................................... 27

Figure 59.

Output reference to Vcc ............................................................. 27

Figure 60.

Split supply ..................................................................... 28

Figure 61.

External supply................................................................... 28

Figure 62.

Schematic for Vocm error ............................................................ 30

Figure 63.

Input current..................................................................... 31

Figure 64.

SHDN pin ...................................................................... 33

Figure 65.

Capacitive load response at Vcc = 3.3 V.................................................. 33

Figure 66.

Capacitive load response at Vcc = 3.3 V with a step of 100 mV .................................. 34

Figure 67.

RC filter when driving ADC........................................................... 34

Figure 68.

Capacitive load response at Vcc = 3.3 V with 720 kHz RC filter .................................. 35

Figure 69.

Capacitive load response at Vcc = 3.3 V with 194 kHz RC filter .................................. 35

Figure 70.

Stability criteria with a serial resistor at VCC = 5 V ........................................... 35

Figure 71.

Start-up time with a decoupling capacitance of 100 nF........................................ 36

Figure 72.

Recommended layout .............................................................. 37

Figure 73.

EMIRR on pin+ ................................................................... 38

Figure 74.

EMIRR on pin- ................................................................... 38

Figure 75.

EMIRR on pin+ (TSC2010H) ......................................................... 38

Figure 76.

EMIRR on pin- (TSC2010H) .......................................................... 38

Figure 77.

Negative overvoltage recovery VCC = ± 2.5 V .............................................. 39

Figure 78.

Positive overvoltage recovery VCC = ± 2.5 V............................................... 39

Figure 79.

H-bridge application ............................................................... 40

Figure 80.

TSC2011H H-bridge application ....................................................... 41

Figure 81.

Solenoid valve application ........................................................... 42

Figure 82.

SO8 package outline ............................................................... 43

TSC2010H, TSC2011H, TSC2012H

List of figures

DS13791 - Rev 1

page 49/50

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