5.6

Capacitive load and stability

Stability analysis must be performed for large capacitive loads over 47 pF; increasing the load capacitance to high

values produces gain peaking in the frequency response, with overshoot and ringing in the step response.

Generally, unity gain configuration is the worst situation for stability and the ability to drive large capacitive loads.

For additional capacitive load drive capability in unity-gain configuration, stability can be improved by inserting

a small resistor RISO (10 Ω to 33 Ω) in series with the output (see Figure 34. Small step overshoot vs. load

capacitance). This resistor significantly reduces ringing while maintaining DC performance for purely capacitive

loads. However, if there is a resistive load in parallel with the capacitive load, a voltage divider is created

introducing a gain error at the output and slightly reducing the output swing. The error introduced is proportional

to the ratio RISO / RL. RISO modifies the maximum capacitive load acceptable from a stability point of view, as

described in Figure 45. Test configuration for RISO:

Figure 45. Test configuration for RISO

Please note that RISO = 33 Ω is sufficient to make the TSV771 and TSV772 stable whatever the capacitive load.

5.7

Resistor values for high speed op amp design

Due to its high gain bandwidth product (GBP), this op amp is particularly sensitive to parasitic impedances.

Board parasitics should be taken into account in any sensitive design. Indeed, excessive parasitic (both capacitive

and inductive) in the op amp frequency range can alter performances and stability. These issues can often be

mitigated by lowering the resistive impedances. More specifically, the RC network created by the schematic

resistors (Rf and Rg) and the parasitic capacitances of both the op amp (as documented in Table 1 to Table 5

and illustrated in Figure 46) and the PCB can generate a pole below or in the same order of magnitude than

the closed-loop bandwidth of the circuit. In this case, the feedback circuit is not able to fully play its role at high

frequency, and the application can be unstable. This issue can happen when the schematic gain is low (typically <

5), or the device is used in follower mode with a resistor in the feedback. In these cases, it is advised to use a low

value feedback resistor (Rf), typically 1 kΩ.

Figure 46. Inverting amplifier configuration with parasitic input capacitances

TSV771, TSV772

Capacitive load and stability

DS13842 - Rev 3

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