AM6546ACD datasheet(7/284 Pages) TI

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4 Revision History

Changes from April 15, 2020 to June 29, 2021 (from Revision A (April 2020) to Revision B

(June 2021))

Page

• GLOBAL: Document Product Status change from "Advanced Information (AI)" to "Production Data (PD)"..... 1

• GLOBAL: Updated the numbering format for tables, figures, and cross-references throughout the document 1

• GLOBAL: Descope of DDRSS; DDR3L and LPDDR4 not supported................................................................1

• (Functional Block Diagram): Updated AM654x, AM652x Block Diagram .......................................................... 5

• (Terminal Configuration and Functions): Updated section title......................................................................... 11

• (Device Information): Updated/Changed table to reflect production part numbers...........................................12

• (Pin Attributes): Updated/Changed PULL UP/DOWN TYPE "TBD" for MMC0 and MMC1 Ball Numbers....... 12

• (Pin Attributes): Updated/Changed "VDDS_OCS0" ro "VDDS_OSC1"............................................................12

• (DDRSS0 Signal Descriptions): Added a footnote reference to DDR_VREF_ZQ............................................ 63

• (DDRSS Signal Mapping): ............................................................................................................................... 66

• (Signal Descriptions): Added note to clarify CPTS signal connection.............................................................. 85

• (Signal Descriptions): Moved MCU CPTS signals from CPSW2G to CPTS section. Moved SYNCn_OUT

signals from SYSTEM to CPTS section. Updated both sets of signal descriptions..........................................85

• Updated CLK frequency unit from "KHz" to "kHz".......................................................................................... 104

• (System0 Signal Descriptions): Added the DESCRIPTION for "GPMC0_FCLK_MUX" SIGNAL NAME....... 104

• (Power Supply Signal Descriptions): Added associated footnotes for CAP_VDDA_1P8_SDIO,

CAP_VDDSHV_SDIO, _1P8_SDIO, and VDDA_3P3_SDIO SIGNAL NAMES............................................. 105

• Updated Reserved Balls Specific Connection Requirements to show MMC0/1_CALPAD should be left floating

on PG2.0 and PG2.1...................................................................................................................................... 121

• (Power-On Hours (POH)): Updated/Changed "TBD" for COMMERCIAL/EXTENDED TEMPERATURE

RANGE "LIFETIME (POH)" for OPP_TURBO ...............................................................................................127

• (Recommended Operating Conditions): Deleted the "Maximum peak-to-peak supply noise" for

VDD_DLL_MMC0/1........................................................................................................................................ 127

• (Analog ADC DC Electrical Characteristics): Updated/Changed the INL MAX value to "±4" LSB................. 134

• (3-3V MODE): Added VIH and VIL rows for MMC0_* and MMC1_* signals with MIN voltage values.............137

• Updated/Changed the associated footnotes, added "VDDS stands for …." and removed the (VIHSS) and

(VILSS) footnotes............................................................................................................................................. 137

• Added System Timing Conditions, Safety Error Signals Switching Characteristics table, Clock Timing

Requirements, and Clock Switching Characteristics under System Timing .................................................. 146

• Added Safety Error Signals Switching Characteristics table under Reset Electrical Data/Timing .................146

• Updated description and limits in Timing Requirements for LVDSRX and added Timing Conditions table....165

• Added timing conditions table for CPSW2G MDIO, RMII, and RGMII. Removed transition time parameters

from individual timing requirements and switching characteristics tables.......................................................165

• (RGMII Timing Requirements): Updated input hold time for RD and RXCTL to 1.15 ns................................ 168

• Updated description of CSI2 ..........................................................................................................................170

• Updated pulse width in DSS to 0.475*P......................................................................................................... 172

• Renamed eHRPWM to ePWM. Added Timing Conditions table. Updated Timing Requirements and Switching

Characteristics titles and parameter descriptions for eCAP, ePWM, and eQEP timing sections....................173

• Added GPIO Timing Conditions table............................................................................................................. 177

• Updated Timing specification values in GPMC: Added Timing Conditions table and removed jitter, slew rate,

and duty cycle information from Switching Characteristics table and diagrams. Also updated CLK parameter

to tc(clk).......................................................................................................................................................... 178

• Added Timing Conditions table and updated Timing specification values in HYPERBUS ............................ 199

• (I2C Timing): Removed timing and switching characteristics tables from I2C section, and added conformance

to Philips Semiconductors I2C-Bus™ Specification, version 2.1 with notes on exceptions............................201

• (MCAN Timing): Added Timing Conditions table and updated value for Tdx to 15 ns....................................202

• (McASP Timing): Added timing conditions table for McASP...........................................................................202

• Added MCSPI timing conditions table. Updated Timing Requirements and Switching Characteristics tables.....

206

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AM6548, AM6528, AM6546, AM6526

SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021

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