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AM6546ACD 数据表(PDF) 85 Page - Texas Instruments |
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AM6546ACD 数据表(HTML) 85 Page - Texas Instruments |
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85 / 284 page  Table 6-47. MMCSD1 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MMC1_DAT0(1) (2) MMC/SD Data IO D28 MMC1_DAT1(1) (2) MMC/SD Data IO E27 MMC1_DAT2(1) (2) MMC/SD Data IO D26 MMC1_DAT3(1) (2) MMC/SD Data IO D27 (1) When MMCSD0 or MMCSD1 is used, any non-MMC signal function multiplexed with the respective pins are not available. This is due to the MMC having an internal IO multiplexer which is controlled by MMCSD0/1_SS_PHY_CTRL_1_REG[31] IOMUX_ENABLE. This internal IO multiplexer is primary for the signal functions associated with MMCSD pins, and the PADCONFIG’s MUXMODE is secondary. Additionally, the internal IO multiplexer affects all of the MMCSD0 or MMCSD1 pins, regardless of configured data bus width. Therefore, when MMCSD0/1_SS_PHY_CTRL_1_REG[31] IOMUX_ENABLE = 0, the respective MMCSD pins are configured for eMMC/SD functionality, regardless of the PADCONFIG [MUXMODE] setting. (2) Each of these signals should have an external 50kΩ pull-up resistor connected to the corresponding power supply. 6.3.18 CPTS Note Some CPTS signals are connected directly to CPTS modules within the device. Other CPTS signals are connected to the Time Sync Router and fanned out to peripherals linked to the router. Input signals are sent to the peripherals while output signals are sourced from the peripherals. For more information, see the Time Sync and Compare Events section in the Time Sync chapter in the device TRM. 6.3.18.1 MCU Domain Table 6-48. CPTS0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_CPTS0_RFT_CLK CPTS Reference Clock I AB3 MCU_CPTS0_TS_COMP CPTS Time Stamp Counter Compare from MCU_CPSW0_CPTS0 O AB4 MCU_CPTS0_TS_SYNC CPTS Time Stamp Counter Bit from MCU_CPSW0_CPTS0 O AC5 MCU_CPTS0_HW1TSPUSH CPTS Hardware Time Stamp Push 1 input to Time Sync Router and MCU_CPSW0_CPTS0 I AC2 MCU_CPTS0_HW2TSPUSH CPTS Hardware Time Stamp Push 2 input to Time Sync Router and MCU_CPSW0_CPTS0 I AC1 6.3.18.2 MAIN Domain Table 6-49. CPTS0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] CPTS0_RFT_CLK CPTS Reference Clock I D21 CPTS0_TS_COMP CPTS Time Stamp Counter Compare from NAVSS0_CPTS0 O AF13 CPTS0_TS_SYNC CPTS Time Stamp Counter Bit from NAVSS0_CPTS0 O AG12 CPTS0_HW1TSPUSH CPTS Hardware Time Stamp Push 1 input to Time Sync Router I B21 CPTS0_HW2TSPUSH CPTS Hardware Time Stamp Push 2 input to Time Sync Router I E21 SYNC0_OUT CPTS Time Stamp Generator Bit 0 from Time Sync Router O D21 SYNC1_OUT CPTS Time Stamp Generator Bit 1 from Time Sync Router O A22 www.ti.com AM6548, AM6528, AM6546, AM6526 SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 85 Product Folder Links: AM6548 AM6528 AM6546 AM6526 |
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