AM6546ACD datasheet(170/284 Pages) TI

170 / 284 page

NO.

PARAMETER

MODE

MIN

TYP

MAX

UNIT

RGMII1

toh(TD-TXC)

Output hold time, RGMII[x]_TD[3:0] valid after

RGMII[x]_TXC high/low

10/100 Mbps

1.2

1000 Mbps

1.05(1)

toh(TX_CTL-TXC)

Output hold time, RGMII[x]_TX_CTL valid after

RGMII[x]_TXC high/low

10/100 Mbps

1.2

1000 Mbps

1.05(1)

(1)

1000Mbps operation requires that the 4 data pins (RGMII[x]_TD[3:0]) and RGMII[x]_TX_CTL have their board propagation delays

matched to within 50 ps of RGMII[x]_TXC.

RGMII[x]_TXC

(A)

RGMII[x]_TD[3:0]

(B)

RGMII[x] TX_CTL

(B)

RGMII9

1st Half-byte

TXERR

TXEN

2nd Half-byte

RGMII7

RGMII8

RGMII6

RGMII10

TXC is delayed internally before being driven to the RGMII[x]_TXC pin. This internal delay is always enabled.

Data and control information is received using both edges of the clocks. RGMII_TD[3:0] carries data bits 3-0 on the rising edge of

RGMII_TXC and data bits 7-4 on the falling edge of RGMII_TXC. Similarly, RGMII_TX_CTL carries TXDV on rising edge of RGMII_TXC

and RTXERR on falling edge of RGMII_TXC.

Figure 7-37. CPSW2G Transmit Interface Timing RGMII Mode

For more information, see section Gigabit Ethernet MAC (MCU_CPSW0) in the device TRM.

7.9.5.3 CSI2

Note

For more information, see section Camera Adapter Layer (CAL) Subsystem in the device TRM.

The camera adaptation layer (CAL) delas with the processing of pixel data coming from an external image

sensor and data from memory. It is a key component for the following multimedia applications: camera

viewfinder, video record, and still image capture.

The device includes one instantiation of CAL Subsystem named CALSS0, with a single companion

CAMERARX0 instance.

CALSS0 is a very flexible subsystem that enables 3 different connections to cameras. It supports MIPI CSI-2

over D-PHY serial interface; a LVDS serial interface; and a traditional parallel interface.

The CALSS0 is compliant with the MIPI D-PHY RX specification v1.01.00 and the MIPI CSI-2 specification, with

4 data differential lanes plus 1 clock differential lane in synchronous mode, double data rate:

• 1.2 Gbps (600 MHz) for each lane.

7.9.5.4 DDRSS

For more details about features and additional description information on the device DDR4 Memory Interfaces,

see the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description.

The device has dedicated interfaces to DDR4 SDRAM. It supports JESD79-4B standard-compliant DDR4

SDRAM devices with the following features:

• 16-bit or 32-bit data path to external SDRAM memory

• Memory device capacity: Up to 8 GB address space available over one chip select

Table 7-32 and Figure 7-38 present switching characteristics for DDRSS.

AM6548, AM6528, AM6546, AM6526

SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021

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