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AM6546 数据表(PDF) 104 Page - Texas Instruments |
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AM6546 数据表(HTML) 104 Page - Texas Instruments |
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104 / 284 page  6.3.26.2 Clock 6.3.26.2.1 MAIN Domain Table 6-68. Clock1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] OSC1_XI High frequency oscillator input I C22 OSC1_XO High frequency oscillator output O E22 6.3.26.2.2 WKUP Domain Table 6-69. Clock0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] WKUP_LFOSC0_XI Low frequency (32.768 kHz) oscillator input I AE4 WKUP_LFOSC0_XO Low frequency (32.768 kHz) oscillator output O AC4 WKUP_OSC0_XI High frequency oscillator input I AD5 WKUP_OSC0_XO High frequency oscillator output O AE6 6.3.26.3 System 6.3.26.3.1 MAIN Domain Table 6-70. System0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] EXT_REFCLK1 External clock input to Main Domain, routed to Timer clock muxes as one of the selectable input clock sources for Timer/WDT modules, or as reference clock to MAIN_PLL2 (PER1 PLL) I A22 GPMC0_FCLK_MUX GPMC functional clock output selected through a mux logic O R28 NMIn External Interrupt I F18 OBSCLK0 Observation clock output for test and debug purposes only O C23 PORz Main Domain cold reset I E19 PORz_OUT Main Domain POR status output O C19 REFCLK0N SERDES Differential Clock Output (negative) O AF9 REFCLK0P SERDES Differential Clock Output (positive) O AF10 REFCLK1N SERDES Differential Clock Output (negative) O AE8 REFCLK1P SERDES Differential Clock Output (positive) O AE9 RESETSTATz Main Domain warm reset status output O D19 RESETz Main Domain warm reset I F17 SOC_SAFETY_ERRORn Error signal output from Main Domain ESM IO E20 SYSCLKOUT0 SYSCLK0 output from Main PLL controller (divided by 4) for test and debug purposes only O B22 6.3.26.3.2 WKUP Domain Table 6-71. System0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_BYP_POR MCU Bypass reset circuitry input. 0 = Internal POR is used, 1 = External MCU_PORz signal is used. I V5 MCU_CLKOUT0 Reference clock output for Ethernet PHYs (50MHz or 25MHz) O AB2 AM6548, AM6528, AM6546, AM6526 SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021 www.ti.com 104 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AM6548 AM6528 AM6546 AM6526 |
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