•

Select CF in order to place FZ1 below FLC (typically 0.1*FLC)

•

Select CP in order to place FP1 at 0.5*FSW

CF= 1

2π⋅RF⋅0.1⋅fLC;CP= 1

2π⋅RF⋅0.5⋅fSW

(22)

The resultant control loop and other transfer functions gain are shown in Figure 18. Type II compensation - Bode

plot .

Figure 18. Type II compensation - Bode plot

f Z1

f LC

f ZESR

f BW

f P1

E/A gain

G

LOOP,II

G

COMP,II

G

LC,II

6.4

Thermal considerations

The thermal design is important to prevent the thermal shutdown of device if junction temperature goes above

170 °C (typ.). The three different sources of losses within the device are:

•

conduction losses due to the non-negligible RDS(on) of the power switch; these are equal to

PHS,ON=RHS,ON⋅D⋅ IOUT2

(23)

where D is the duty cycle of the application and RHS, ON is the maximum power MOSFET on-resistance. Note that

the duty cycle is theoretically given by the ratio between VOUT and VIN, but actually it is slightly higher in order to

compensate the losses of the regulator. So the conduction losses increase compared with the ideal case;

•

switching losses due to power MOSFET turn ON and OFF; these can be calculated as:

PHS,SW=VIN⋅IOUT⋅ TRISE+TFALL

2 ⋅fSW≅VIN⋅IOUT⋅TTR⋅fSW

(24)

where TRISE and TFALL are the overlap times of the voltage across the power switch (VDS) and the current flowing

into it during turn-ON and turn-OFF phases.

TTR is the equivalent switching time. For this device the typical value for the equivalent switching time is 40 ns.

•

Quiescent current losses, calculated as

ALED6000

Thermal considerations

DS13018 - Rev 4

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