List of figures

Figure 1.

Functional block diagram - L5050S ...................................................... 2

Figure 2.

Functional block diagram - L5050SD ..................................................... 3

Figure 3.

Pins configuration .................................................................. 4

Figure 4.

Output voltage vs TJ ................................................................ 8

Figure 5.

Output voltage vs Vs ................................................................ 8

Figure 6.

Output voltage vs Ven ............................................................... 8

Figure 7.

Drop voltage vs output current ......................................................... 8

Figure 8.

Current consumption vs output current ................................................... 8

Figure 9.

Current consumption vs output current (at light load condition) ................................... 8

Figure 10.

Current consumption vs input voltage (Io = 0.15 mA) .......................................... 9

Figure 11.

Current consumption vs input voltage (Io = 50 mA) ........................................... 9

Figure 12.

Current limitation vs TJ .............................................................. 9

Figure 13.

Current limitation vs input voltage ....................................................... 9

Figure 14.

Short-circuit current vs TJ............................................................. 9

Figure 15.

Short-circuit current vs input voltage ..................................................... 9

Figure 16.

VEn_high vs TJ .................................................................... 10

Figure 17.

VEn_ low vs TJ .................................................................... 10

Figure 18.

PSRR ......................................................................... 10

Figure 19.

Application schematic - L5050S ....................................................... 11

Figure 20.

Application schematic - L5050SD - common input voltage ..................................... 12

Figure 21.

Application schematic - L5050SD - double supply line for the input voltages ......................... 12

Figure 22.

Stability region ................................................................... 13

Figure 23.

Maximum load variation response ...................................................... 13

Figure 24.

SO-8 PC board for L5050S .......................................................... 14

Figure 25.

SO-8 PC board for L5050SD ......................................................... 14

Figure 26.

Rthj-amb vs PCB copper area in open box free air condition.................................... 15

Figure 27.

SO-8 thermal impedance junction ambient single pulse (L5050S) ................................ 15

Figure 28.

SO-8 thermal impedance junction ambient single pulse (one channel on for L5050SD) ................. 15

Figure 29.

L5050S thermal fitting model of a Vreg in SO-8 ............................................. 16

Figure 30.

L5050SD Thermal fitting model of a Vreg in SO-8 ........................................... 16

Figure 31.

SO-8 package outline .............................................................. 18

Figure 32.

SO-8 recommended footprint (dimensions are in mm) ........................................ 19

Figure 33.

SO-8 tape and reel shipment (suffix “TR”) ................................................ 20

L5050

List of figures

DS13704 - Rev 3

page 24/25