3

Device overview

3.1

Main features

•

Capability to operate in dual-chip mode in master/slave configuration, user-selectable via NVM programming

•

Internal 16 MHz oscillator for timing generation

•

Internal 10 MHz oscillator for monitoring

•

Dedicated CLKIN pin to provide an external 4 MHz clock, 1% accurate, to improve timing accuracy (by FLL

circuitry)

•

Dedicated CLKSW pin to optimize switching regulator operation phases between master and slave devices

(output when master, input when slave)

•

Phase configuration for switching regulators time base, user-programmable via Global SPI

•

Integrated temporal watchdog control

•

RESET_N reset input/output pin (output with pull-up and pull-down capability when master, input with

pull-down capability when slave)

•

Internal NVM, used for trimming and device configuration, user-programmable via Global SPI

3.2

SPI interface

•

One dedicated 32-bit SPI bus for global configuration and control

•

One dedicated 32-bit SPI bus for remote sensor configuration and control, SafeSPI v1.0 compatible

3.3

Power supply and energy reserve management

•

Integrated 2 MHz SYS boost regulator, 10 V ±8% nominal output

•

Integrated 2 MHz energy reserve boost regulator, 33 V ±6% or 23.5 V ±6% nominal output, user-selectable

via Global SPI

•

Integrated energy reserve capacitor charge current-limited switch

•

Integrated energy reserve capacitor discharge overcurrent-protected switch

•

Integrated energy reserve crossover current-limited switch

•

Crossover switch “active” signal (output when master, input when slave)

•

Integrated 2 MHz synchronous SAT buck regulator, 8 V ±4% or 6.5 V ±4% nominal output, user-selectable

via NVM programming

•

Integrated 2 MHz synchronous VCC buck regulator, 3.3 V ±3% nominal output; 50% fixed duty-cycle mode

(FDM), selectable via NVM programming

•

External microcontroller core supply voltage monitoring (VCOREMON), user-selectable via NVM

programming

•

V5 linear regulator with external power PNP transistor, 5 V ±5% nominal output; possibility to disable via

NVM programming

•

Switching frequency selection via Global SPI

•

Over and undervoltage status monitorings

•

Open feedback diagnostic on VCC buck and V5 linear regulators

•

Switching regulator ground loss detection and shutdown

•

Boost external diode loss detection and voltage clamping

•

Overtemperature detection and shutdown on all switching regulators, ER crossover switch and ER charge

switch

•

Energy reserve diagnostics, capacitor value and ESR

3.4

Safing FET regulator and diagnostics

•

Dual integrated 18 V linear regulators for high-side safing FET source voltage, enabled via arming logic

•

Safing FET connection integrity diagnostics

•

Battery and energy reserve diode integrity diagnostics

L9690

Device overview

DB4806 - Rev 2

page 13/24