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FDA803D-EHT 数据表(PDF) 51 Page - STMicroelectronics |
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FDA803D-EHT 数据表(HTML) 51 Page - STMicroelectronics |
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51 / 78 page ![]() DocID031487 Rev 2 51/78 FDA803D I2S bus interface 77 13 I2S bus interface The device receives the audio signal through I2S bus. The I2S bus is composed of three lines: Clock line (I2Sclk pin); Word Select line (I2Sws pin); Serial Data line (I2Sdata pin). The Word Select line frequency must be always equal to the audio sampling frequency fs. According to the I2C setting of IB1[7-5], the device supports the following standards for sampling frequency: 44.1 kHz; 48 kHz; 96 kHz; 192 kHz. According to the I2C setting of IB0[6-5], the user can send the audio signal with the following data formats: I2S standard (max fs = 192 kHz); TDM - 4CHs (max fs = 192 kHz); TDM - 8CHs (max fs = 96 kHz); TDM - 16CHs (max fs = 48 kHz). For all the mentioned data formats, the user must provide the data word following two's complement representation, starting from the MSB. The data word is composed of 32 bits: the device processes only the first 24 most significant bits, while it does not care the least significant 8 bits. The internal PLL locks on the Clock line signal: when the I2S clock is missing or corrupted, the PLL consequently unlocks and the device forces the finite state machine in standby state. Furthermore, since the Clock line frequency is dependent on I2S bus configuration, it is strictly necessary to configure the I2C bits IB0[6-5] and IB1[7-5] accordingly. |
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