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FDA803U 数据表(PDF) 49 Page - STMicroelectronics |
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FDA803U 数据表(HTML) 49 Page - STMicroelectronics |
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49 / 76 page ![]() DS12497 Rev 2 49/76 FDA803U Additional features 75 Please note that, by limiting the PWM duty cycle, a limitation of the output power occurs: the output power in case of usage of LRF function decreases about 10 % @ 1 % THD. 11.2 Noise gating Noise gating is an automatic noise reduction feature that activates when output signal reaches not audible levels. When input signal levels falls below -109 dBFs, the system activity is automatically optimized in order to exploit very low noise level on the output speakers. The noise gating process has a 500 ms watching time before turning on, in order to avoid spurious activations. The feature is enabled by default and can be disabled selecting IB3[1]. 11.3 Dither PWM The device implements a function, Dither PWM, which can be enabled through I2C bus by setting IB1[2]. The main target of this feature is to improve the EMC performances in the range [10 – 30 MHz], especially in MUTE condition. The function consists in modulating the period of the output PWM. The function doesn’t affect the average PWM frequency. The modulation pattern is repeated every 8 PWM clock cycles, in order to avoid introducing significant noise in the audio bandwidth. A qualitative example of the function operation is depicted in Figure 62. Figure 62. Dither PWM effect on output PWM |
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