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TDA7808 数据表(PDF) 23 Page - STMicroelectronics |
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TDA7808 数据表(HTML) 23 Page - STMicroelectronics |
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23 / 39 page  DS12230 Rev 4 23/39 TDA7808 I2S and TDM bus interface 38 7.4 Timings requirements Figure 30. Audio interface timing Table 8. I2S interface timing Symbol Parameter note min max unit Fsck0 SCK (bit clock) frequency - - 49.152 MHz - SCK (bit clock) frequency tolerance - 0.9Fsck0 1.1Fsck0 MHz Tsck SCK period - 20 - ns - SCK duty cycle - 40 60 % Tsckh SCK high time - 6 - ns Tsckl SCK low time - 6 - ns - SCK transition time - - 4 ns - WS (word select) frequency - - 192 KHz Twsh WS high time I2S standard 25 or 32 Tsck (duty cycle=50%) ns Twsh WS high time TDM 4- channel 1 Tsck 127 Tsck ns Twsh WS high time TDM 8-16- channel 1 Tsck 255 Tsck ns Tws WS setup time - 5 - ns Twh WS hold time - 6 - ns Tds SD13 SD24 (data inputs) setup time before SCK rising edge -5- ns Tdh SD13 SD24 (data inputs) hold time after SCK rising edge -6- ns |
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