L9788 datasheet(49/264 Pages) STMICROELECTRONICS

49 / 264 page

DS12308 Rev 4

49/264

L9788

Watchdog

263

Figure 18. WDA state flow

Each time the watchdog error counter is EC > 7 counter PWR_CNT counter increases.

When this counter is PWR_CNT=7 and a further error occurs, the power-latch will be

terminated if KEY_IN is low. The PWR_CNT-counter is not cleared when EC <7.

PWR_CNT-counter is cleared when EC < 5 or by RST_UV.

The monitoring module works independently of the controller functionality. The monitoring

module generates various questions, which the controller must fetch and correctly respond

to within a defined time window. The monitoring module checks whether the response is

returned in a time window and if the response is fully correct.

The question is a 4-bit word. This 4-bit word can be fetched by the controller using a read

access to register WDA REQULO. The monitoring module also calculates the expected

correct response, which is compared to the actual response from the controller.

The response is a 32-bit word consisting of the 4 bytes RESP_BYTE3, RESP_BYTE2,

RESP_BYTE1 and RESP_BYTE0. The 4 bytes are sent to the monitoring module via MSC

in the order RESP_BYTE3 - RESP_BYTE2 - RESP_BYTE1 - RESP_BYTE0 using four

times the command WDA_RESP - once for each answer byte.

The monitoring cycle phase is initialized by (the end of) writing of RESP_BYTE0 (least

significant response byte) or by a write access to the RESPTIME register. The cycle starts

with a variable wait time (response time, set by register RESPTIME), followed by a fixed

time window. When a monitoring cycle ends (the end of the fixed time window has been

reached) a new monitoring cycle is started automatically.

A correct response within the time window (at a response time > 0 ms) decreases an

ERROR COUNTER by one. An incorrect response, a response outside the time window or

response time = 0 ms leads to the incrementing of the ERROR COUNTER by one.

Power

Down

Safety loads = disabled

WDA pin = Low

Power On and Reset release

Configure WDA Time Window and

Request first Query

Write Answer

Answer0

Answer1

Right

Answer ?

Decrement ERR_CNT

yes

ERR_CNT < 5

Safety Loads = Enabled

WDA pin = High

RST_CNT = 0

yes

WDA Sequencer starts

WDA Time Reference

yes

Increment RST_CNT

ERR_CNT > 7

KEY OFF?

yes

RST_CNT = 0

PWR_CNT = 0

yes

Generate Reset

Drive RST pin to Low

PWR_CNT > 7

Increment ERR_CNT

Increment PWR_CNT (max 7)

yes

INIT_WDR=1 ?

yes

Generate next Query

GADG2511161203PS

RST_CNT =7

(Typ 64 kHz +/-5%)

ERR_CNT = 6

PWR_CNT = 0

Request for Query

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