6

Application information

The device should be properly decoupled with 100 nF capacitors connected electrically and physically close to

each power supply pin (VDD and VSS); the other terminal of the capacitor being connected to the ground plane. In

order to obtain the best performance of the device, a proper layout should be done in order to minimize the impact

of parasitic inductance to avoid significant LdI/dt overshoot voltages. Trace length should be minimized. If the

application is switching DC signals, adding decoupling capacitors on the S or D pins connected to these sources

is also a good practice. Unused analog pins (Di, iS1, iS2) can either be left floating or connected to ground (or

any other fixed voltage compatible with the operating table). Digital pins (SELi and INH) must be connected to

either 0 V or VDD. It is recommended to solder the exposed pad to a copper plane on PCB at VSS potential to

obtain a better thermal impedance (but it can also be left open). When used for gain selection of an inverting gain

amplification stage, it is recommended to place the switch directly on the inverting pin of the op amp (and not

on the other side of Rg resistor). Indeed, as the input common mode voltage is fixed, the voltage on the analog

switch is constant on all the channels, regardless of the analog signal being amplified. Therefore, even if the gain

is reduced because of the Ron (-Rf/(Ron+Rg)), it is not modulated by its flatness which is not null.

STG1218

Application information

DS13729 - Rev 3

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