8

Layout

8.1

Layout guidelines and considerations

In order to optimize the PCB layout, the following considerations should be taken into account:

•

SMT ceramic capacitors (or different types of low-ESR and low-ESL capacitors) must be placed close to

each supply rail pins. A 100 nF capacitor must be placed between VDD and GND and between VH and

GNDISO, as close as possible to device pins, in order to filter high-frequency noise and spikes. In order to

provide local storage for pulsed current, a second capacitor with a value between 1 µF and 10 µF should

also be placed close to the supply pins.

•

It is good practice to add filtering capacitors close to logic inputs of the device (IN+, IN-), particularly for fast

switching or noisy applications.

•

The power transistors must be placed as close as possible to the gate driver to minimize the gate loop area

and inductance that might carry noise or cause ringing.

•

To avoid degradation of the isolation between the primary and secondary side of the driver, there should not

be any trace or conductive area below the driver.

•

If the system has multiple layers, it is recommended to connect the VH and GNDISO pins to internal ground

or power planes through multiple vias of adequate size. These vias should be located close to the IC pins to

maximize thermal conductivity.

8.2

Layout example

An example of STGAP2SiCSC half-bridge suggested PCB layout with main signals highlighted by different colors

is shown in Figure 11. It is recommended to follow this example for correct positioning and connection of filtering

capacitors.

Figure 11. Half-bridge suggested PCB layout

Q1

Q2

U1

U2

CVH1

CVH2

CVDD1

ROFF

RON

G1

D1

S1

CIN

RIN

CVH1

CVH2

CVDD1

ROFF

RON

G2

D2

S2

CIN

RIN

TOP

BOTTOM

STGAP2SICS

Layout

DS13402 - Rev 4

page 13/22