STUSB1702 datasheet(16/38 Pages) STMICROELECTRONICS

16 / 38 page

Figure 6. Write operation

Address

n+1

Start bit = SDA falling when SCL = 1

Stop bit = SDA rising when SCL = 1

Restart bit = start after a start

Address

n+2

Start

Device addr

7 bits

W A Reg address

8 bits

A Reg data

8 bits

Reg data

8 bits

Reg data

8 bits

Stop

5.2

Timing specifications

The device uses a standard slave I²C channel at speed up to 400 kHz.

Table 11. I²C timing parameters - VDD = 5 V

Symbol

Parameter

Min.

Typ.

Max.

Unit

Fscl

SCL clock frequency

400

kHz

thd,sta

Hold time (repeated) START condition

0.6

μs

tlow

LOW period of the SCL clock

1.3

thigh

HIGH period of the SCL clock

0.6

tsu,dat

Set-up time for repeated START condition

0.6

thd,dat

Data hold time

0.04

0.9

tsu,dat

Data setup time

100

Rise time of both SDA and SCL signals

20 + 0.1 Cb

300

Fall time of both SDA and SCL signals

20 + 0.1 Cb

300

tsu,sto

Set-up time for STOP condition

0.6

μs

tbuf

Bus free time between a STOP and START condition

1.3

Capacitive load for each bus line

400

Figure 7. I²C timing diagram

SDA

Vil

thd,sta

SCL

tlow

thd,dat

tsu,dat thigh

tsu,sta

Vih

STUSB1702

Timing specifications

DS12664 - Rev 1

page 16/38

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