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CF9501A 数据表(PDF) 9 Page - Nippon Precision Circuits Inc

部件名 CF9501A
功能描述  Radio Controlled Clock Receiver IC
PDF  10 Pages
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制造商  NPC [Nippon Precision Circuits Inc]
网页  http://www.npc.co.jp/en
标志 NPC - Nippon Precision Circuits Inc

CF9501A 数据表(HTML) 9 Page - Nippon Precision Circuits Inc

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SM9501A/B
NIPPON PRECISION CIRCUITS INC.—9
Crystal Filter Circuit
External crystals are used as filters. Multiple frequencies (40kHz and 60kHz) are supported by connecting
crystals in parallel. The center frequency and bandwidth of the filters is determined by the crystal characteris-
tics. If the center frequency is lower than the target frequency, C
×40 and C×60 can be added to change the res-
onant frequency. And R
×40 and R×60 can be added to adjust the filter Q factor. Internally, pin XO is linked to
pin XI by a phase-inverted signal passed through a capacitor, which cancels the high-frequency components
that pass through the crystal parallel capacitances.
Detector Circuit
The amplified signal is full-wave rectified and passed through a lowpass filter detector. The detector output is
input to peak hold (pin CP) and bottom hold (pin CB) circuits to form the decoder reference potentials and
peak hold potential for AGC control.
Decoder Circuit
The detector output and peak/bottom hold mid-level potential reference are used to decode the time code sig-
nal, which is output on pin OUT. The output is active-LOW, so that the output is LOW when the input ampli-
tude is HIGH.
Standby Function
When PON is open (or HIGH), the device is in standby mode and the current consumption is reduced. Receiver
operation starts when PON goes LOW.
PON
Mode
OUT
Open (or HIGH)
Standby
HIGH
LOW
Operating
Time code
XO
Rx40
Rx60
Cx40
Cx60
40kHz
60kHz
XI
Amplifier
Rectifier
LPF
Peak/
Bottom
Hold
Bottom hold
Peak hold
VSS potential
VSS potential
VSS potential
Bottom hold
Peak hold
Mid-level potential
Decoder
OUT output
VSS potential
LPF waveform
VDD potential
VSS potential
VSS potential
Rectifier
LPF
Peak/
Bottom
Hold



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