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MM54HC166 数据表(PDF) 3 Page - National Semiconductor (TI) |
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MM54HC166 数据表(HTML) 3 Page - National Semiconductor (TI) |
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3 / 6 page ![]() AC Electrical Characteristics CL e 50 pF tr e tf e 6 ns unless otherwise noted TAe25 C 74HC 54HC Symbol Parameter VCC TAeb40 Cto a85 CTAeb55 Cto a125 C Units Typ Guaranteed Limits fMAX Maximum 20V 6 5 42 MHz Operating Frequency 45V 31 25 21 MHz 60V 36 29 25 MHz tPHL Maximum Propagation 20V 140 175 210 ns tPLH Delay Clock to QH 45V 14 28 35 42 ns 60V 24 30 36 ns tPHL Maximum Propagation 20V 130 165 195 ns tPLH Delay Clear to Qh 45V 11 26 35 39 ns 60V 22 30 33 ns tsu Minimum Setup Time 20V 80 100 120 ns ShiftLoad to Clock 45V 16 20 24 ns 60V 14 18 20 ns tsu Minimum Setup Time 20V 80 100 120 ns Data before Clock 45V 16 20 24 ns 60V 14 18 20 ns tREM Minimum Removal 20V 0 0 0 ns Time Clear to Clock 45V 0 0 0 ns 60V 0 0 0 ns th Maximum Hold Time 20V 0 0 0 ns Data after Clock 45V 0 0 0 ns 60V 0 0 0 ns tr tf Maximum Output 20V 75 95 110 ns Rise and Fall Time 45V 7 15 19 22 ns 60V 13 16 19 ns tw Minimum Pulse 20V 80 100 120 ns Width Clock or Clear 45V 16 20 24 ns 60V 14 16 20 ns Cpd Power Dissipation (per 100 pF Capacitance (Note 5) package) Cin Maximum Input 510 10 10 pF Capacitance AC Electrical Characteristics VCC e 5V CL e 15 pF TA e 25 C tr e tf e 6 ns unless otherwise noted Symbol Parameter Typical Guaranteed Limits Units fMAX Maximum 31 MHz Operating Frequency tPHL Maximum Propagation 16 ns tPLH Delay Clock to Qh tPHL Maximum Propagation 12 ns tPLH Delay Clear to Qh tsu Minimum Setup Time ShiftLoad High 16 ns to Clock tsu Minimum Setup Time 16 ns Data before Clock tREM Minimum Removal Time 0ns Clear to Clock th Maximum Hold Time 0ns Data after Clock tw Minimum Pulse 16 ns Width Clock or Clear Note 5 Cpd determines the no load dynamic power consumption PD e CPD VCC2 f a ICC VCC and the no load dynamic current consumption IS e CPD VCC f a ICC 3 |
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