TLF5770

August 1989

MM54HC166MM74HC166

8-Bit Parallel InSerial Out Shift Registers

General Description

The MM54HC166MM74HC166 high speed 8-BIT PARAL-

LEL-INSERIAL-OUT SHIFT REGISTER utilizes advanced

silicon-gate CMOS technology It has low power consump-

tion and high noise immunity of standard CMOS integrated

circuits along with the ability to drive 10 LS-TTL loads

These Parallel-In or Serial-In Serial-Out shift registers fea-

ture gated CLOCK inputs and an overriding CLEAR input

The load mode is established by the SHIFTLOAD input

When high this input enables the SERIAL INPUT and cou-

ples the eight flip-flops for serial shifting with each clock

pulse When low the PARALLEL INPUTS are enabled and

synchronous loading occurs on the next clock pulse During

parallel loading serial data flow is inhibited Clocking is ac-

complished on the low-to-high level edge of the CLOCK

pulse through a 2-input NOR gate permitting one input to

be used as a clock enable or CLOCK INHIBIT function

Holding either of the clock inputs high inhibits clocking

holding either low enables the other clock input This allows

the system clock to be free running and the register can be

stopped on command with the other clock input The

CLOCK INHIBIT input should be changed to the high level

only while the clock input is high A direct CLEAR input over-

rides all other inputs including the CLOCK and sets all flip-

flops to zero

The 54HC74HC logic family is functionally as well as pin

out compatible with the standard 54LS74LS logic family

All inputs are protected from damage due to static dis-

Features

Y

Typical propagation delay

Y

Wide operating supply voltage range 2V – 6V

Y

Y

Low quiescent supply current 80 mA maximum

(74HC Series)

Y

Fanout of 10 LS-TTL loads

Connection Diagram

Dual-In-Line Package

TLF5770 – 1

Order Number MM54HC166 or MM74HC166

Function Table

Inputs

Internal

Output

Clear

Shift

Clock

Clock Serial

Parallel

Outputs

Load Inhibit

AH

LX

X

X

X

X

L

L

L

HX

L

L

X

X

HL

L

u

X

ah

a

b

h

HH

L

u

HX

HH

L

u

LX

HX

H

u

XX

a

steady-state input conditions were established

u

transition of the clock

C1995 National Semiconductor Corporation

RRD-B30M105Printed in U S A