5.8

Unused channel

When one of the two channels of the TSB7192 and TSB7192A is not used, it must be properly connected in order

to avoid internal oscillations that can negatively impact the signal integrity on the other channel, as well as the

current consumption. Two different configurations can be used:

•

Gain configuration: the channel can be set in gain at which the stability is guaranteed (+10/-9 or more). The

•

Comparator configuration: the channel can be set to a comparator configuration (without negative feedback).

In this case, positive and negative inputs can be set to any value provided that these values are significantly

different (100 mV or more, to avoid oscillations between positive and negative state) and the differential

input is lower than the maximum specified in the operating range (maximum 2 V), or the input current is

limited to less than 10 mA to avoid damaging the circuit.

5.9

Maximum power dissipation

The usable output load current drive is limited by the maximum power dissipation allowed by the device package.

The absolute maximum junction temperature for the TSB7191, TSB7191A, TSB7192 and TSB7192A is 150 °C.

The junction temperature can be estimated as follows:

TJ=PD×Rtℎ−ja+TA

(10)

by the output stage transistor. It is calculated as follows:

PD= VCC×ICC + VCC+−VOUT ×ILoad

(11)

when the op-amp sources the current

PD= VCC×ICC + VOUT−VCC− ×ILoad

(12)

when the op-amp is sinks the current.

Do not exceed the 150 °C maximum junction temperature for the device. Exceeding the junction temperature limit

can cause degradation in the parametric performance or even destroy the device.

5.10

PCB layout recommendations

Particular attention must be paid to the layout of the PCB tracks connected to the amplifier, load, and power

supply. The power and ground traces are critical as they must provide adequate energy and grounding for all

circuits. The best practice is to use short and wide PCB traces to minimize voltage drops and parasitic

inductance. In addition, to minimize parasitic impedance over the entire surface, a multi-via technique that

connects the bottom and top layer ground planes together in many locations is often used. The copper traces

connecting the output pins to the load and supply pins should be as wide as possible to minimize trace resistance.

5.11

Decoupling capacitor

In order to ensure op-amp full functionality, it is mandatory to place a decoupling capacitor of at least 22 nF as

close as possible to the op-amp supply pin. A good decoupling helps to reduce electromagnetic interference

impact.

TSB7191, TSB7191A, TSB7192, TSB7192A

Unused channel

DS12641 - Rev 5

page 22/34