Analog Integrated Circuit Device Data

Freescale Semiconductor

9

33975

DYNAMIC ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 5. Dynamic Electrical Characteristics

Characteristic

Symbol

Min

Typ

Max

Unit

SWITCH INPUT

Pulse Wetting Current Time

15

16

22

ms

Interrupt Delay Time

Normal Mode

–

5.0

16

µs

Sleep Mode Switch Scan Time

100

200

300

µs

Calibrated Scan Timer Accuracy

Sleep Mode

–

–

10

%

Calibrated Interrupt Timer Accuracy

Sleep Mode

–

–

10

%

DIGITAL INTERFACE TIMING (12)

Required Low State Duration on VPWR for Reset (13)

–

–

10

µs

Falling Edge of CS to Rising Edge of SCLK

Required Setup Time

100

–

–

ns

Falling Edge of SCLK to Rising Edge of CS

Required Setup Time

50

–

–

ns

SI to Falling Edge of SCLK

Required Setup Time

16

–

–

ns

Falling Edge of SCLK to SI

Required Hold Time

20

–

–

ns

SI, CS, SCLK Signal Rise Time (14)

–

5.0

–

ns

SI, CS, SCLK Signal Fall Time (14)

–

5.0

–

ns

Time from Falling Edge of CS to SO Low Impedance (15)

–

–

55

ns

Time from Rising Edge of CS to SO High Impedance (16)

–

–

55

ns

Time from Rising Edge of SCLK to SO Data Valid (17)

–

25

55

ns

Notes

12.

These parameters are guaranteed by design. Production test equipment uses 4.16 MHz, 5.0 V SPI interface.

13.

This parameter is guaranteed by design but not production tested.

14.

Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.

15.

Time required for valid output status data to be available on SO terminal.

16.

Time required for output states data to be terminated at SO terminal.

17.

Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load.