SPC574S60 datasheet(47/77 Pages) STMICROELECTRONICS

47 / 77 page

DS10601 Rev 6

47/77

SPC574Sx

Electrical characteristics

All the Flash operations require the presence of the system clock for internal

synchronization. About 50 synchronization cycles are needed: this means that the timings of

the previous table can be longer if a low frequency system clock is used.

3.15

PLL0/PLL1 electrical characteristics

The device provides a phase-locked loop (PLL0) as well as a frequency-modulated phase-

locked loop (PLL1) module to generate a fast system clock from the main oscillator driver.

Table 29. Flash memory Life Specification

Symbol

Characteristics(1)

Value

Unit

Min

Typ

NCER16K 16 KB CODE Flash endurance

—

100

—

Kcycles

NCER32K 32 KB CODE Flash endurance

—

100

—

Kcycles

NCER64K 64 KB CODE Flash endurance

—

100

—

Kcycles

NCER256K 256 KB CODE Flash endurance

—

100

—

Kcycles

NDER16K 16 KB EEPROM Flash endurance

100

—

Kcycles

tDR1k

Minimum data retention Blocks with 0 - 1,000 P/E cycles

—

Years

tDR10k

Minimum data retention Blocks with 1,001 - 10,000 P/E cycles

—

Years

tDR100k Minimum data retention Blocks with 10,001 - 100,000 P/E cycles 15

—

Years

1. Program and erase cycles supported across specified temperature specs.

Table 30. PLL1 electrical characteristics

Symbol

Parameter

Conditions(1)

Value

Unit

Min

Typ

Max

fPLLIN SR — PLL1 reference clock(2)

—

37.5

—

78.125 MHz

ΔPLLIN SR —

PLL1 reference clock duty

cycle(2)

—35

—

fPLLOUT CC D PLL1 output clock frequency

—

4.762

—

625

MHz

fVCO(3) CC P VCO frequency

—

600

—

1250 MHz

tLOCK CC P PLL1 lock time

Stable oscillator (fPLLIN =16 MHz)

—

µs

ΔtSTJIT CC T PLL1 short term jitter

fPLLIN = 16 MHz (resonator),

fPLLCLK @ 64 MHz

——

1.8

IPLL

CC C PLL1 consumption

TA =25°C

—

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = -40 to 125 °C, unless otherwise specified.

2. PLLIN clock retrieved directly from FXOSC clock. Input characteristics are granted when oscillator is used in functional

mode. When bypass mode is used, oscillator input clock should verify fPLLIN and ΔPLLIN.

3. Frequency modulation is considered ±2%.

SPC574S60 数据表(PDF) 47 Page - STMicroelectronics

SPC574S60 数据表(HTML) 47 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77

数据表下载

链接网址

SPC574S60 数据表(PDF) 47 Page - STMicroelectronics

SPC574S60 数据表(HTML) 47 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77

数据表 下载

链接网址

数据表下载