Figure 11. Receiver output rise and fall times and propagation delay

0V

VL

A

RE

VO

50%

tPLH

tPHL

VI

VO

10%

90%

tr

tf

VL

1V5

B

VI

0 V

VOL

VOH

50%

90%

10%

Figure 12. Receiver enable/disable times with driver enabled

1 kΩ ±1%

CL=15 pF±20%

VL

VI

50 Ω

50%

tPZH(1)

VI

VO

VL

50%

VOL

0V

VL

≈ 0V

tPHZ

90%

VO

50%

50%

tPZL(1)

10%

tPLZ

VOH

D at VL

S1 to GND

D at OV

S1 to VL

STR485

Test circuits and typical characteristics

DS12713 - Rev 1

page 13/24