Figure 14. Type III compensation - Bode plot

f Z1

f LC

f ZESR

f BW

f P1

E/A gain

G

LOOP,III

G

COMP,III

G

LC,III

f Z2

f P2

6.5

Thermal considerations

The thermal design prevents the thermal shutdown of the device if junction temperature goes above 170 °C (typ.).

The three different sources of losses within the device are:

•

conduction losses due to the non-negligible RDS(on) of the power switch; these are equal to

PHS,ON=RHS,ON⋅D⋅ IOUT2

(29)

where D is the duty cycle of the application and RHS,ON is the maximum resistance overtemperature of the power

switch. Note that the duty cycle is theoretically given by the ratio between VOUT and VIN, but actually it is quite

higher in order to compensate the losses of the regulator. So the conduction losses increase compared with the

ideal case;

•

switching losses due to power MOSFET turn-ON and OFF; these can be calculated as:

PHS,SW=VIN⋅IOUT⋅ TRISE+TFALL

2 ⋅fSW≅VIN⋅IOUT⋅TTR⋅fSW

(30)

where TRISE and TFALL are the overlap times of the voltage across the power switch (VDS) and the current flowing

into it during turn-ON and turn-OFF phases. TTR is the equivalent switching time. For this device the typical value

for the equivalent switching time is 40 ns.

•

Quiescent current losses, calculated as follows:

PQ=VIN⋅IQOPVIN+VBIAS⋅IQOPVBIAS

(31)

where IQOPVIN and IQOPVBIAS are the A7987 quiescent current in case of separate bias supply. If the switch-over

feature is not used, the IC quiescent current is the only one from VIN, IQUIESC, as summarized in

Table 5. Electrical characteristics. The junction temperature TJ can be calculated as the equation below:

A7987

Thermal considerations

DS12928 - Rev 3

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