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VIPERGAN65 数据表(PDF) 19 Page - STMicroelectronics |
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VIPERGAN65 数据表(HTML) 19 Page - STMicroelectronics |
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19 / 35 page ![]() The required delay to exactly synchronize the Turn-On at the valley, TDELAY,canbecalculatedasbelow: Equation 5 (5) TDELAY=TVALLEY−TZCD−DELAY In the equation TZCD−DELAYrepresentsthedelaybetweenthedemagnetizationtimeandtheinstantoftimein which the ZCD voltage crosses the triggering threshold VZCDT:thisdelayisintherangeoffewtensnsupto hundred ns but can be easily experimentally measured during converter’s operation. The value of VTBcanbedirectlyreadfromthecurvealso. Once VTB voltage is known, the value of the resistor can be easily derived: Equation 6 (6) RDELAY= RTB NAUXNSEC∙VOUTVTB−1 The resistor RTBcanbecalculatedasreportedinDynamicblankingtime. The TDELAYissettothedefaultvaluewhenRDELAYislowerthan: Equation 7 (7) RDELAY_default< RTB NAUXNSEC∙ VOUT VD−ONMIN −1 Dynamic blanking time and valley synchronization functions can be disabled connecting TB to GND. The decision if the function is used or not is taken at power-up: before the pin VDD reaches the VDD-ON threshold, the current ITB-DIS (200 µA typ.) is sourced from the pin. If the TB pin voltage is below the VTB-DIS threshold (100 mV typ.), the pin is assumed to be connected to GND, the related circuitry is disabled, and the information is latched until the next power-on. Please note that to ensure a correct check of the disabling function, the resistor RDELAYcannotbelowerthan: Equation 8 (8) RDELAYmin <VTB−DISmax ITB−DISmin =750 Ω 5.9 TB pin configuration The pin TB can be easily configured in different combinations, as reported in Table 6 and in Figure 21, Figure 22, Figure 23, Figure 24. Table 6. TB pin matrix configuration Dynamic Blanking Time Valley Synchronization Schematic Configuration Yes Yes Figure 21 No Yes Figure 22 Yes No Figure 23 No No Figure 24 VIPERGAN65 TB pin configuration DS14005 - Rev 2 page 19/35 |
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