• Output ripple

• Component count

• Lowest noise

Typical applications that have input voltages of ≤ 6 V use a 2.2-MHz switching frequency. Applications that have

input voltages > 6 V can be optimized for efficiency using a 1-MHz switching frequency. In this case, the output

voltage ripple doubles, which is typically acceptable when powering high speed ADCs. Optimization for powering

clock and PLL circuits that need a 3.3-V output use a 2.2-MHz switching frequency, minimizing output voltage

ripple and low frequency noise.

For the application cases that are not found in Table 8-2, there are two methods to design the TPSM8291x

circuit. Section 8.2.2.1 uses Webench to design the circuit automatically or the calculations in Section 8.2.2.2

can be used instead.

Table 8-2. Typical Single L-C Filter Design Recommendations

DESIGN GOAL

VIN

VOUT

FSW

OUTPUT CAPACITORS

(2)

Typical

12 V

(1)

≤ 2.0 V

(1)

1 MHz

3 × 22 µF, 10 V, 0805

Higher efficiency (with

higher ripple and noise)

12 V

2.0 V < VOUT ≤ 3.3 V

1 MHz

3 × 22 µF, 10 V, 0805

Low ripple, noise PLL and

Clock Supply

12 V

2.6 V ≤ VOUT ≤ 3.3 V

2.2 MHz

3 × 22 µF, 10 V, 0805

Typical

12 V

> 3.3 V

2.2 MHz

Typical

5 V

≤ 3.3 V

2.2 MHz

3 × 22 µF, 10 V, 0805

Typical

5 V

> 3.3 V

2.2 MHz

1 × 47 µF, 1210 and 2 ×

22 µF, 10 V, 0805

(1)

The maximum input to output voltage difference is limited by the device maximum minimum on-time of 70 ns. This is especially

important for input voltages above 12 V or output voltages below 1 V. See Section 8.2.2.2.1.

(2)

For output capacitor part numbers, see Table 8-4.

The second stage L-C filter is optional, as the device can be used without this filter to achieve below 20-μVRMS

noise typically. A second stage filter is added to provide additional attenuation of the output voltage ripple. The

output voltage is sensed after the second L-C filter by connecting the FB resistors to the second stage L-C filter

capacitor. This action provides remote sense, minimizing output voltage drop due to the ferrite bead. Refer to

Table 8-3 for second stage L-C filter recommendations based on the output voltage.

Table 8-3. Second Stage L-C (Ferrite Bead) Filter Design Recommendations

VOUT (V)

FERRITE BEAD IMPEDANCE (AT 100 MHZ)

(2)

OUTPUT CAPACITORS (1)

≤ 3.3 V

8 Ω to 20 Ω

2 × 22 µF, 10 V, 0805

> 3.3 V

8 Ω to 20 Ω

3 × 22 µF, 10 V, 0805

(1)

For output capacitor part numbers, see Table 8-4.

(2)

For second stage L-C filter part numbers, see Table 8-5.

8.2.2 Detailed Design Procedure

If the specific design is not found in the Table 8-2 section, TI recommends WEBENCH® to generate the design.

Alternatively, the manual design procedure in External Component Selection can be followed.

8.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPSM8291x device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost.

3. Open the advanced tab to optimize for output voltage ripple.

4. After in a TPSM8291x design, enable the second stage L-C filter and change other settings from the

drop-down on the left.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

www.ti.com

TPSM82913

SLVSGJ4A – OCTOBER 2022 – REVISED DECEMBER 2022

Copyright © 2022 Texas Instruments Incorporated

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