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AS5045 数据表(PDF) 7 Page - ams AG |
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AS5045 数据表(HTML) 7 Page - ams AG |
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7 / 24 page  AS5045 12-BIT PROGRAMMABLE MAGNETIC ROTARY ENCODER Revision 1.5 www.austriamicrosystems.com Page 7 of 24 3.7 Timing Characteristics 3.7.1 Synchronous Serial Interface (SSI) (operating conditions: Tamb = -40 to +125°C, VDD5V = 3.0~3.6V (3V operation) VDD5V = 4.5~5.5V (5V operation) unless otherwise noted) Parameter Symbol Min Typ Max Unit Note Data output activated (logic high) t DO active 100 ns Time between falling edge of CSn and data output activated First data shifted to output register tCLK FE 500 ns Time between falling edge of CSn and first falling edge of CLK Start of data output T CLK / 2 500 ns Rising edge of CLK shifts out one bit at a time Data output valid t DO valid 357 375 394 ns Time between rising edge of CLK and data output valid Data output tristate t DO tristate 100 ns After the last bit DO changes back to “tristate” Pulse width of CSn t CSn 500 ns CSn = high; To initiate read-out of next angular position Read-out frequency fCLK >0 1 MHz Clock frequency to read out serial data 3.7.2 Pulse Width Modulation Output (operating conditions: Tamb = -40 to +125°C, VDD5V = 3.0~3.6V (3V operation) VDD5V = 4.5~5.5V (5V operation) unless otherwise noted) Parameter Symbol Min Typ Max Unit Note 232 244 256 Signal period = 4097µs ±5% at Tamb = 25°C PWM frequency f PWM 220 244 268 Hz = 4097µs ±10% at Tamb = -40 to +125°C Minimum pulse width PW MIN 0.95 1 1.05 µs Position 0d; Angle 0° Maximum pulse width PW MAX 3891 4096 4301 µs Position 4095d; Angle 359.91° Note: when OTP bit “PWMhalfEn” is set, the PWM pulse width PW is doubled (PWM frequency fPWM is divided by 2) 3.8 Programming Conditions (operating conditions: Tamb = -40 to +125°C, VDD5V = 3.0~3.6V (3V operation) VDD5V = 4.5~5.5V (5V operation) unless otherwise noted) Parameter Symbol Min Typ Max Unit Note Programming enable time t Prog enable 2 µs Time between rising edge at Prog pin and rising edge of CSn Write data start t Data in 2 µs Write data valid t Data in valid 250 ns Write data at the rising edge of CLK PROG Load Programming data t Load PROG 3 µs Rise time of VPROG before CLKPROG t PrgR 0 µs Hold time of VPROG after CLK PROG t PrgH 0 5 µs Write data – programming CLK PROG CLK PROG 250 kHz ensure that VPROG is stable with rising edge of CLK CLK pulse width t PROG 1.8 2 2.2 µs during programming; 16 clock cycles Hold time of Vprog after programming t PROG finished 2 µs Programmed data is available after next power-on Programming voltage, pin PROG V PROG 7.3 7.4 7.5 V Must be switched off after zapping Programming voltage off level V ProgOff 0 1 V Line must be discharged to this level Programming current I PROG 130 mA during programming Analog Read CLK CLKAread 100 kHz Analog Readback mode |
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