2

ICS950402

0700B—04/30/04

Pin Descriptions

PIN #

PIN NAME

PIN

TYPE

DESCRIPTION

1

*FS0/REF0

I/O

Frequency select latch input pin / 14.318 MHz reference clock.

2

VDDREF

PWR

Ref, XTAL power supply, nominal 3.3V

3

X1

IN

Crystal input, Nominally 14.318MHz.

4

X2

OUT

Crystal output, Nominally 14.318MHz

5

GND

PWR

Ground pin.

6

*(PCICLK7/HTTCLK0)ModeA

I/O

PCI clock output / Hyper Transport output / Mode selection pin, this input is activated by the

ModeB selection pin.

7

*PCICLK8/HTTCLK1/ModeB

I/O

PCI clock output / Hyper Transport output / Mode selection latch input pin.

8

PCICLK9/HTTCLK2

OUT

PCI clock output / Hyper Transport output.

9

VDDPCI

PWR

Power supply for PCI clocks, nominal 3.3V

10

GND

PWR

Ground pin.

11

~PCICLK10/HTTCLK3

OUT

PCI clock output / Hyper Transport output.

12

PCICLK11

OUT

PCI clock output.

13

PCICLK0

OUT

PCI clock output.

14

PCICLK1

OUT

PCI clock output.

15

GND

PWR

Ground pin.

16

VDDPCI

PWR

Power supply for PCI clocks, nominal 3.3V

17

****PCICLK2

OUT

Real time system reset signal for watchdog timer timeout. This signal is active low and

selected by Mode latch input / 3.3V PCI clock clock output.

18

****PCICLK3

I/O

Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low / PCI clock

output, this output is activated by the Mode selection pin

19

VDDPCI

PWR

Power supply for PCI clocks, nominal 3.3V

20

GND

PWR

Ground pin.

21

PCICLK4

OUT

PCI clock output.

22

PCICLK5

OUT

PCI clock output.

23

~*PCICLK_F/ModeC

I/O

Free running PCI clock not affected by PCI_STOP# / Mode selection latch input pin.

24

~*(PCICLK6)PCI_STOP#

I/O

PCI clock output, this output is activated by the Mode selection pin / Stops all PCICLKs

besides the PCICLK_F clocks at logic 0 level, when input low.

25

SCLK

IN

Clock pin of I2C circuitry 5V tolerant

26

SDATA

I/O

Data pin for I2C circuitry 5V tolerant

27

GND

PWR

Ground pin.

28

24_48MHz/Sel24_48#*~

I/O

24/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 = 24MHz.

29

AVDD48

PWR

Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V

30

GND

PWR

Ground pin.

31

48MHz/FS3**

I/O

Frequency select latch input pin / Fixed 48MHz clock output. 3.3V

32

VDD

PWR

Power supply, nominal 3.3V

33

GND

PWR

Ground pin.

34

GND

PWR

Ground pin.

35

VDDCPU

PWR

Supply for CPU clocks, 3.3V nominal

36

CPUCLK8C1

OUT

"Complimentary" clocks of differential 3.3V push-pull K8 pair.

37

CPUCLK8T1

OUT

"True" clocks of differential 3.3V push-pull K8 pair.

38

VDDCPU

PWR

Supply for CPU clocks, 3.3V nominal

39

GND

PWR

Ground pin.

40

CPUCLK8C0

OUT

"Complimentary" clocks of differential 3.3V push-pull K8 pair.

41

CPUCLK8T0

OUT

"True" clocks of differential 3.3V push-pull K8 pair.

42

GND

PWR

Ground pin.

43

VDDA

PWR

3.3V power for the PLL core.

44

Reset#

OUT

Real time system reset signal for frequency gear ratio change or watchdog timer timeout.

This signal is active low.

45

REF2/FS2*

I/O

14.318 MHz reference clock / Frequency select latch input pin.

46

VDDREF

PWR

Ref, XTAL power supply, nominal 3.3V

47

GND

PWR

Ground pin.

48

REF1/FS1*

I/O

14.318 MHz reference clock / Frequency select latch input pin.

* Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ This Output has 2X Drive Strength

**** This Output has 2.3X Drive Strength