P89LPC952FA datasheet(21/66 Pages) PHILIPS

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9397 750 14716

Preliminary data sheet

Rev. 01— 16 September 2005

21 of 66

Philips Semiconductors

P89LPC952

8-bit microcontroller with 10-bit ADC

7.2 Enhanced CPU

The P89LPC952 uses an enhanced 80C51 CPU which runs at six times the speed of

standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most

instructions execute in one or two machine cycles.

7.3 Clocks

7.3.1 Clock deﬁnitions

The P89LPC952 device has several internal clocks as deﬁned below:

OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four clock

sources (see Figure 5) and can also be optionally divided to a slower frequency (see

Section 7.8 “CCLK modiﬁcation: DIVM register”).

Note: fosc is deﬁned as the OSCCLK frequency.

CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per machine

cycle, and most instructions are executed in one to two machine cycles (two or four CCLK

cycles).

RCCLK — The internal 7.373 MHz RC oscillator output. The clock doubler option, when

enabled, provides an output frequency of 14.746 MHz.

PCLK — Clock for the various peripheral devices and is CCLK

⁄

7.3.2 CPU clock (OSCCLK)

The P89LPC952 provides several user-selectable oscillator options in generating the CPU

clock. This allows optimization for a range of needs from high precision to lowest possible

cost. These options are conﬁgured when the ﬂash is programmed and include an on-chip

watchdog oscillator, an on-chip RC oscillator, an oscillator using an external crystal, or an

external clock source. The crystal oscillator can be optimized for low, medium, or high

frequency crystals covering a range from 20 kHz to 18 MHz.

7.3.3 Low speed oscillator option

This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic

resonators are also supported in this conﬁguration.

7.3.4 Medium speed oscillator option

This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic

resonators are also supported in this conﬁguration.

7.3.5 High speed oscillator option

This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic

resonators are also supported in this conﬁguration. When using a clock frequency

above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit

is required to hold the device in reset at power-up until VDD has reached its

speciﬁed level. When system power is removed VDD will fall below the minimum

speciﬁed operating voltage. When using a clock frequency above 12 MHz, in some

applications, an external brownout detect circuit may be required to hold the device

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