P89LPC952FA datasheet(30/66 Pages) PHILIPS

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9397 750 14716

Preliminary data sheet

Rev. 01— 16 September 2005

30 of 66

Philips Semiconductors

P89LPC952

8-bit microcontroller with 10-bit ADC

and the RTC is enabled. If the internal RC oscillator is used to clock the RTC during

power-down, there will be high power consumption. Please use an external low frequency

clock to achieve low power with the RTC running during power-down.

7.16 Reset

The P1.5/RST pin can function as either an active-LOW reset input or as a digital input,

P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to ‘1’, enables the external

reset input function on P1.5. When cleared, P1.5 may be used as an input pin.

Remark: During a power-up sequence, The RPE selection is overridden and this pin

always functions as a reset input. An external circuit connected to this pin should not

hold this pin LOW during a power-on sequence as this will keep the device in reset.

After power-up this input will function either as an external reset input or as a digital input

as deﬁned by the RPE bit. Only a power-up reset will temporarily override the selection

deﬁned by RPE bit. Other sources of reset will not override the RPE bit.

Reset can be triggered from the following sources:

• External reset pin (during power-up or if user conﬁgured via UCFG1);

• Power-on detect;

• Brownout detect;

• Watchdog timer;

• Software reset;

• UART break character detect reset.

For every reset source, there is a ﬂag in the Reset Register, RSTSRC. The user can read

this register to determine the most recent reset source. These ﬂag bits can be cleared in

software by writing a ‘0’ to the corresponding bit. More than one ﬂag bit may be set:

• During a power-on reset, both POF and BOF are set but the other ﬂag bits are

cleared.

• For any other reset, previously set ﬂag bits that have not been cleared will remain set.

7.16.1 Reset vector

Following reset, the P89LPC952 will fetch instructions from either address 0000H or the

Boot address. The Boot address is formed by using the boot vector as the high byte of the

address and the low byte of the address = 00H.

The Boot address will be used if a UART break reset occurs, or the non-volatile Boot

Status bit (BOOTSTAT.0) = 1, or the device is forced into ISP mode during power-on (see

P89LPC952 User’s Manual). Otherwise, instructions will be fetched from address 0000H.

7.17 Timers/counters 0 and 1

The P89LPC952 has two general purpose counter/timers which are upward compatible

with the standard 80C51 Timer 0 and Timer 1. Both can be conﬁgured to operate either as

timers or event counters. An option to automatically toggle the T0 and/or T1 pins upon

timer overﬂow has been added.

In the ‘Timer’ function, the register is incremented every machine cycle.

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