Data Sheet

ADM3061E/ADM3062E/ADM3063E/ADM3064E/

ADM3065E/ADM3066E/ADM3067E/ADM3068E

SPECIFICATIONS

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Rev. H | 5 of 25

Table 3.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

Low

VOL

0.4

V

VIO = 3.6 V, output current (IOUT) = 2 mA,

VID4 ≤ −0.2 V

0.4

V

VIO = 2.7 V, IOUT = 1 mA, VID ≤ −0.2 V2

0.2

V

VIO = 1.95 V, IOUT = +500 µA, VID ≤ −0.2 V2

High

VOH

2.4

V

VIO = 3.0 V, IOUT = −2 mA, VID ≥ −0.03 V

2.0

V

VIO = 2.3 V, IOUT = −1 mA, VID ≥ −0.03 V2

VIO − 0.2

V

VIO = 1.65 V, IOUT = −500 µA, VID ≥ −0.03 V2

Short-Circuit Current

85

mA

VOUT = GND or VIO

Three-State Output Leakage

IOZR

±2

µA

RO pin = 0 V or VIO

1 VIO = VCC for ADM3061E/ADM3063E/ADM3065E/ADM3067E.

2 ADM3062E/ADM3064E/ADM3066E/ADM3068E only.

3 ADM3063E/ADM3064E/ADM3067E/ADM3068E only.

4 VID is the receiver input differential voltage.

TIMING SPECIFICATIONS

ADM3061E/ADM3062E/ADM3063E/ADM3064E

VCC = 3.0 V to 5.5 V, VIO = 1.62 V to VCC (ADM3062E/ADM3064E), TA = TMIN (−40°C) to TMAX (+125°C), unless otherwise noted. All typical

specifications are at TA = 25°C, VIO = VCC = 3.3 V, unless otherwise noted.

Table 4.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

DRIVER

Maximum Data Rate1

500

kbps

Propagation Delay

tDPLH, tDPHL

220

800

ns

RLDIFF capacitor = 54 Ω, CL1 capacitor = CL2 capacitor = 100 pF,

see Figure 5 and Figure 40

Skew

tDSKEW

5

100

ns

RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 5 and Figure 40

Rise/Fall Times

tDR, tDF

120

300

800

ns

RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 5 and Figure 40

Enable to Output High

tDZH

100

1000

ns

RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41

Enable to Output Low

tDZL

100

1000

ns

RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41

Disable Time from Low

tDLZ

350

2000

ns

RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41

Disable Time from High

tDHZ

600

2000

ns

RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41

Enable Time from Shutdown to High

tDZH(SHDN)2

550

2000

ns

RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41

Enable Time from Shutdown to Low

tDZL(SHDN)2

550

2000

ns

RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41

RECEIVER

Maximum Data Rate

500

kbps

Propagation Delay

tRPLH, tRPHL

200

ns

CL = 15 pF, |VID| ≥ 1.5 V, VCM = 1.5 V, see Figure 7 and Figure 42

Skew/Pulse Width Distortion

tRSKEW

50

ns

CL = 15 pF, |VID| ≥ 1.5 V, VCM = 1.5 V, see Figure 7 and Figure 42

Enable to Output High

tRZH

10

50

ns

RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, DE high, see Figure 8 and

Figure 44

Enable to Output Low

tRZL

10

50

ns

RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, DE high, see Figure 8 and

Figure 44

Disable Time from Low

tRLZ

10

50

ns

RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and Figure 44

Disable Time from High

tRHZ

10

50

ns

RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and Figure 44

Enable from Shutdown to High

tRZH(SHDN)3

2000

ns

RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and Figure 43