Rev. C 03/22

5

PFS5173-5178/5274

www.power.com

Functional Description

The HiperPFS-5 family are variable switching frequency boost PFC

devices. It employs a constant amp-second on-time and constant

volt-second off-time control algorithm. This algorithm is used to

regulate the output voltage and shape the input current to comply

with regulatory harmonic current limits and (high power factor).

Integrating the switch current and controlling it to have a constant

amp-second product over the on-time of the switch allows the

average input current to follow the input voltage. Integrating the

difference between the output and input voltage maintains a constant

volt-second balance dictated by the electro-magnetic properties of

the boost inductor and thus regulates the output voltage and power.

More specifically, the controller sets a constant value of charge

delivered during each on-cycle of the PowiGaN switch. The charge

per cycle is altered gradually over many switching cycles in response

to load changes so it can be considered constant across a given half

line cycle. With this constant charge (or amp-second) control, the

following relationship is therefore also true:

I

IN × tON = K2 (1)

The control technique also sets constant volt-second for the off-time

(t

OFF). The off-time is controlled such that:

(V

O – VIN) × tOFF = K1 (2)

Since the volt-seconds during the on-time must equal the volt-second

during the off-time, to maintain flux equilibrium in the PFC choke, the

on-time (t

ON) is controlled such that:

V

IN × tON = K1 (3)

Substituting t

ON from (3) into (1) gives:

I

IN = VIN × K2/K1 (4)

The relationship of (4) demonstrates that by controlling a constant

amp-second on-time and constant volt-second off-time, the input

current I

IN is proportional to the input voltage VIN, satisfying the

fundamental requirement for power factor correction.

At the end of volt-second integration for the off-time, the control

engine waits for the valley of the Drain voltage, and turns on the

PowiGaN at the minimum of the valley. In order to compensate for

this delay, the HiperPFS-5 IC also measures the difference between

desired OFF-time (controlled by volt-second integration) and actual

OFF-time (synchronized with Drain voltage valley). The control

engine then adjusts the next On-time period to account for this

difference. This valley correction ensures the same average current

in each switching cycle.

This control produces a discontinuous mode power-switch current

waveform (during normal operation) that varies both in frequency and

peak current value across a line half-cycle to produce an input current

proportional to the input voltage.

Control Engine

The controller features a low bandwidth, high gain OTA error-amplifier

of the non-inverting terminal of which is connected to an internal

voltage reference of 3.85 V. The inverting terminal of the error-

amplifier is fed from the external FEEDBACK pin which connects to

the output voltage divider network with a divider ratio of 3.85:400 to

regulate the output voltage to 400 V (nominal). The FEEDBACK pin

connects directly to the divider network to ensure fast transient load

response.

The difference between the input and output voltage is derived

internally, and the result is scaled, integrated, and compared to a

voltage reference (V

OFF) to determine the point of off-time

termination. The controller delays this request and terminates the

off-time at a point to coincide with the nearest valley of the ring on

the drain voltage.

The internally sensed FET switch current is scaled by the input-

voltage peak detector current-sense gain (M

ON) then integrated and

compared with the error-amplifier signal (V

E) to determine the

on-time termination point. The valley correction block adjusts this to

compensate for the delay imposed by the valley switching adjustment

in the off-time.

Line Feed-Forward Scaling Factor (MON) and PF Enhancer

The VOLTAGE MONITOR (V) pin voltage is sampled and converted by

a ∆-Σ ADC to a quantized digital value. A digital line-cycle peak

detector, with dynamic time constants and multi-cycle filtering,

derives and averages the peak of the input line voltage. This peak is

used internally to scale the gain of the current sense signal through

the M

ON variable. This contribution is required to reduce the dynamic

range of the control feedback signal as well as flatten the loop gain

over the operating input line voltage. The line-sense feed-forward

gain adjustment is proportional to the square of the peak rectified AC

line voltage and is adjusted as a function of the VOLTAGE MONITOR

pin voltage.

At high-line and light load, the feed-forward M

ON variable is

dynamically adjusted across the line cycle in order to compensate for

the line current distortion caused by the EMI filter and full bridge

network, and improve power factor.

The line-sense feed-forward gain is also important in providing a

switch power limit over the input line range.

Beyond the specified maximum power rating of the device, the

internal power limit will regulate the output voltage below the set

regulation threshold as a function of output overload to maintain

constant output power.

IS dt

VERR

VOFF

(VO – VIN)dt

Latch

RESET

Latch

SET

Gate

Drive (Q)

Maximum

ON-time

Minimum

OFF-time

Timing

Supervisor

Valley Synchronization

In a normal operation, the PowiGaN switch is turned-on at the valley

of the drain voltage of the PowiGaN power switch. The Valley

Synchronisation Block ensures turn-on in the valley to minimize

turn-on losses.

The voltage measured across the auxiliary (sense) winding of the PFC

inductor is connected to the VALLEY SENSING VS pin through an

external resistor. This voltage of auxiliary (sense) winding of the PFC

inductor represents the difference between of the voltage on the

drain of the PowiGaN switch and the rectified voltage. The valleys of

this voltage coincide with valleys of the voltage on the drain of the

PowiGaN switch.

Figure 5. Idealized Converter Waveforms.