Rev. C 03/22

8

PFS5173-5178/5274

www.power.com

EcoSmart (Frequency Sliding and Spread-

Spectrum Switching)

The HiperPFS-5 IC’s include an EcoSmart function whereby the

internal error signal (V

ERR) is used to detect the converter output

power. This is used to set the average switching frequency as a

function of output power.

As shown in the Figure 9 below, the off-time integrator control

reference (V

OFF) is set by the internal error-voltage level (output

power) to allow the converter to maintain output voltage regulation

and flat conversion efficiency from 20% to 100% of rated load, which

is essential to meet many efficiency directives. The degree of frequency

slide is also controlled which is a function of input line voltage. The

lower V

OFF slope as a function of input voltage reduces the average

frequency range for high input line operation. Using this approach,

the HiperPFS-5 IC enables the use of a smaller PFC inductor, while

still keeping the switching frequency below 150 kHz across line and

load to minimize the burden on EMI components.

VA

VIN < 140 VAC

3.05 V

(Full Power)

VIN > 170 VAC

3.05 V 5.2 V

140 VAC

170 VAC

VA

VB

VB

VERR

VIN

PI-7228b-031422

Figure 9. EcoSmart Frequency Sliding V

OFF vs. VERR and VOFF(MAX) vs. Input Voltage.

Power Good Signal For PFS517xF

The HiperPFS-5 features a power good (PG) circuit which comprises

an internal comparator that turns an open-drain switch on during

start-up when the sensed output voltage on the FEEDBACK pin rises

to ~95% (V

PG+) of the output voltage threshold. During start-up,

prior to the output voltage reaching V

PG+, the PG signal is in a

high-impedance state (internal switch is in off-state).

The power good signal transitions from on to off-state when the

sensed output voltage on the FEEDBACK pin falls to a user selected

threshold, programmed via resistor on the POWER GOOD

THRESHOLD (PGT) pin. The POWER GOOD THRESHOLD pin sources

a fixed current I

PGT. This current in combination with the power good

threshold resistor sets the threshold at which the power good signal

transitions from the on-state to the high-impedance off-state as the

PFC output falls out of regulation.

The power good comparator has an internal 81 µs de-glitch filter

(t

PGD) to prevent noise events from falsely triggering the programmed

VPG-threshold.

In the event a load fault prevents the boost from achieving regulation

(above ~95% of the set output voltage threshold) the PG function will

remain in the high-impedance state and so will not indicate when an

output voltage has fallen below the user programmed V

PG- threshold.

The V

PG- user programmed threshold is only enabled once the VPG+

threshold has been reached.

If the POWER GOOD THRESHOLD programming pin is tied to

REFERENCE pin, the power good function is disabled and PG remains

in the high-impedance (off) state. This is the preferred configuration

when PG is not used. If the POWER GOOD THRESHOLD pin is shorted

to the SIGNAL GROUND pin, the PG signal will transition to the

on-state at V

PG+ and remain low (on) until the PFC output voltage has

fallen below the V

FB(UV) threshold for greater than tFB(UV) seconds.

Similar to the disable condition described above, if the value of the

PGT resistor is such that the V

PG- threshold is greater than the VPG+

threshold, the PG signal will latch off and remain in the high-

impedance off-state.