Rev. C 03/22

6

PFS5173-5178/5274

www.power.com

In certain cases, where valley switching is not possible, such as

during operation in CCM, or when the amplitude of oscillations of the

drain voltage becomes too small, the controller enables the No Valley

Switching (NVS) mode. In this condition, the controller does not wait

for the valley to appear. When the volt-second integration circuit

requests a turn-on, it immediately turns on the PowiGaN switch.

Valley Correction

Valley correction reduces the input current distortion coming from the

valley switching operation in discontinuous mode (DCM). Valley

correction is enabled in DCM operation when more than one valley is

detected.

In a DCM PFC converter with valley switching, the PowiGaN switch

can be turned on only at the V

DS valley instants. The relaxation

frequency of the V

DS voltage ring is ≤ 1 MHz, which means that the

time between two valleys are more than 1 µs apart. There is a delay

between the instant when the OFF controller requests the turn-on

and the point when the PowiGaN power switch is actually turned on.

This delay changes the average input current from what was

originally requested by the controller, and the input current becomes

distorted. The deviation in average cycle current from the desired

current is proportional to this delay. In such cases, the switching

period instantly changes by a significant value (could be in the range

of 1 µs) and distortion of the input current is the most pronounced.

Controller Supplying Circuitry

Parts Without Self-Supply Circuit

Parts without the self-supply circuit are supplied only through the

BIAS POWER (VCC) pin. Inside the IC there is a linear regulator

between the VCC pin and the VDR pin. This linear regulator regulates

the voltage on the VDR pin to 5.25 V.

The voltage on the VDR pin is used to supply the internal controller.

A decoupling capacitor is connected to the VDR pin to provide a low

high-frequency impedance path to ground.

Parts With the Self-Supply Circuit

Parts with the self-supply feature generate the internal supply voltage

for the control circuitry. The converter operates with the control

circuitry being supplied through the internal PowiGaN until the

voltage on the VCC pin form the external bias circuit is established.

Once the voltage on the VCC pin appears, and is greater than the

minimum voltage needed to operate the internal linear regulator

(VCC > 7 V), the internal linear regulator will start supplying the

control circuitry and disable the self-supply circuit.

Start-Up With Pin-to-Pin Short-Circuit Protection

At start-up and prior to the commencement of switching, the engine

performs a sequence of operational pin short/open checks, as shown

in Figure 6. If no faults are detected, when the input voltage peak is

above the brown-in threshold, the engine enables switching.

The OTA error amplifier provides a non-linear amplifier (NLA)

mechanism to overcome the inherently slow feedback loop response

when the sensed output voltage on the FEEDBACK pin is outside its

regulation window. This allows the error amplifier function to limit

the maximum overshoot and undershoot during load transient events.

To reduce switch and output diode current stress at start-up, the

HiperPFS-5 calculates the off-time based on the output voltage (V

O)

during start-up, resulting in a soft controlled start-up.

Additionally, the Over-Current Protection (OCP) threshold is ramped

up from 60% to 100% of its nominal value. This reduces flux swing

in the PFC inductor if the control loop requires larger duty cycle.

At power-up, the controller first determines whether the appropriate

supply voltage is applied by checking that the voltage on the VDR pin

is greater than the VDR

UV+ threshold. Once the voltage on the VDR

pin is above the VDR

UV+ threshold, pin open/short tests are

performed, and if the FEEDBACK pin voltage is valid, the over-

temperature status is confirmed to be false.

Once these checks are confirmed, the input voltage is monitored via

the VOLTAGE MONITOR pin until it exceeds the VBR+ threshold (but

the peak detector is not saturated). This is the point at which the

value of the resistor on the POWER SELECTION (PS) pin is determined

and the maximum output power is set. After the maximum power is

determined the switching is enabled.

Yes

Yes

Yes

Yes

Yes

No

No

Yes

Yes

No

No

No

VDR > VDRUV+

(C > 2.5 V) or

Feedback < FBOFF

Reference

Capacitor

Valid?

OTP Fault

Peak Valid and

Peak > VBR+

Feedback > FBOFF

Capacitor Reset

Short C to G

for 230 µs

Remove Current

Source on C Pin,

Short C to G

Apply Current to C Pin

for 65 µs

Remove Short

on C Pin

Remove C to G Short,

Start Switching

PI-9537-021522

Start

Figure 6. Start-up Flow Chart.