Rev. C 03/22

10

PFS5173-5178/5274

www.power.com

Selectable Power Limit

The PS (Power Selection) pin is used to program the output power of

the HiperPFS-5. The power is programmed with a resistor connected

to the G pin, in 10% steps, between 70% to 100% of the nominal

output power.

Turns Ratio For Auxiliary Winding

The VS pin is connected to the auxiliary winding of the PFC inductor

through a resistor to detect the valley switching. This resistor can

adjust the proper delay for a given application so that the turn-on of

the PowiGaN happens at the valley of the voltage on the DRAIN pin.

The delay depends on the resistance of this resistor and the effective

capacitance on the VS pin. If the resistor is closer to the VS pin, the

effective capacitance on the VS pin is smaller with a shorter delay.

Resistor (Ohms)

Power Selection

Comments

>400 k

100%

Leaving pin open is acceptable

100 k – 200 k

90%

25 k – 50 k

80%

<6 k

70%

Connecting pin short to G node is acceptable

Protection Modes

Brown-In Protection

The VOLTAGE MONITOR pin has an input line undervoltage detection

feature to limit the minimum start-up voltage. This detection

threshold will inhibit the device from starting at input voltages below

brown-in point and above input peak voltages of 400 V

PK.

Brown-Out Protection

The VOLTAGE MONITOR pin features a brown-out protection mode

whereby the HiperPFS-5 will turn-off when the VOLTAGE MONITOR

pin voltage is below the line undervoltage threshold (VBR-) for a

period exceeding t

BRWN_OUT (brown-out debounce period). In the event

that a single half-line cycle is assuming (normal operating line

frequency is in the range of 47 Hz to 63 Hz) the brown-out protection

feature will not be activated.

Once brown-out has been triggered, the HiperPFS-5 IC’s soft-

shutdown gradually reduces the internal error-voltage to zero over a

period of 1 ms which ramps the power PowiGaN on-time to zero. The

onset of this soft-shutdown is aligned to the next line cycle zero

crossing to minimize reactive component di/dt transients and allow

time for the energy stored within the boost choke as well as the input

EMI filter to dissipate. This helps minimize voltage transients after

the bridge rectifier and prevent false restarts.

The device will enter an auto-restart, including FMEA pin fault checks

and other start-up qualifications prior to checking that the line voltage

is above the brown-in threshold (VOLTAGE MONITOR pin voltage

above V

BR+).

After a brown-in event, and once the t

STARTUP timer expires, the line

voltage brown-out threshold is reduced to V

BR-NTC and the brown-out

timer is extended to t

BRWN_OUT_NTC to allow for the drop in line voltage

caused by the voltage drop across not due to an in-rush limiting

negative temperature coefficient (NTC) thermistor in series with the

input line.

If the t

BRWN_OUT_NTC debounce timer is triggered by the sensed line

voltage dropping below the V

BR-NTC threshold but the line voltage

recovers to above the V

BR-NTC threshold before the tBRWN_OUT_NTC expires,

Table 2.

Power Programming Resistances (Resistor between PS pin and G pin).

then the t

STARTUP timer will be re-started. If the line does not recover

above the V

BR-NTC threshold before the tBRWN_OUT_NTC debounce timer

expires a shutdown will occur.

After the t

STARTUP timer has expired, if the VOLTAGE MONITOR pin

voltage rises above V

BR-NTC, the brown-out debounce timer will switch

to normal period (t

BRWN_OUT) and the brown-out threshold will switch to

V

BR-. If the VOLTAGE MONITOR pin voltage is not above VBR- after the

subsequent t

BRWN_OUT timer has expired then a brown-out shutdown

will occur.

HiperPFS-5 IC’s incorporates input waveform discrimination to

determine if the line signal peak-to-average voltage ratio is

representative of a sine wave or a high-duty-cycle square wave.

The brown-out threshold is reduced to V

BR_SQ when a high duty cycle

(UPS) square wave is detected.

VCC Undervoltage Protection (UVLO)

The BIAS POWER (VCC) pin has an under-voltage lock-out protection

which inhibits the IC from starting unless the applied VCC voltage is

above the VCC

UVLO+ threshold.

The IC initiates a start-up once the BIAS POWER pin voltage exceeds

the VCC

UVLO+ threshold. After start-up the IC will continue to operate

until the BIAS POWER pin voltage has fallen below the VCC

UVLO- level.

Line Dependent Over-Current Protection (OCP)

The device includes a cycle-by-cycle over-current protection

mechanism which protects the device in the event of a fault. The

OCP circuit protects the internal power switch. This intends to protect

the converter from output short-circuit or overload fault conditions.

The OCP limit is set as a function of the input line voltage. This helps

to restrict power limit due to short-circuits as well as minimize the

stress on the switch due to current overloads at higher input line

conditions.

Figure 13 below illustrates the hysteretic adjustment of the OCP

levels as a function of VOLTAGE MONITOR pin line sense.

Oppositely, if the resistor is put far from the VS pin, then the effective

capacitance on the VS pin is larger with a longer delay. The initial

design recommended value for the resistor is 10 KΩ and put this

resistor close to VS pin.

The maximum turn ratio (N

MAX) of auxiliary winding is calculated as

N

MAX = (VOMIN ‒ VACPEAK)/ VVS1. Here, the VOMIN is minimum output

voltage considering the ripple tolerance. If V

O = 400 V and assuming

3% tolerance, the V

OMIN is 388 V; VACPEAK is the peak voltage of

maximum high-line input. For universal AC input, V

ACPEAK =

√2 × 265 ≈ 375 V; V

VS1 is the valley sensing positive threshold with

typical value 0.88 V. From the above equation, it can calculate the

maximum turn ratio (N

MAX) is about 15. The recommended turns ratio

for auxiliary winding is ranged from 10 to 15.