PFS7323L datasheet(10/30 Pages) POWERINT

10 / 30 page

Rev. D 06/15

PFS7323-7329

www.power.com

Temporarily reducing the brown-out threshold prevents false

turn-off at high power start-up when voltage drop across the

input bridge rectifier and filter stage may cause the rectified

input to sag below the brown-out threshold.

Increasing the brown-out timer during soft-start permits a longer

time for an in-line AC-side NTC to reduce its resistance and

increase the voltage presented to the VOLTAGE MONITOR pin.

In the event the converter does not reach regulation at start-up

(overload or power limit condition) C

UV protection threshold is

not activated and both the I

UV(SS) and tUV(SS) are not reset.

It is expected that while the input voltage peak is below the

brown-out threshold (I

UV-) during a line cycle drop out or line sag

event the internal peak detector will force refresh the line feed-

forward gain (m

ON) to the minimum value at the tREFRESH sample

rate.

Similar to the original HiperPFS, the controller latches the OCP

threshold in the event of an AC line cycle drop-out when the

peak sense is for a high input line condition (V

IN > 170 VAC).

Fast Output Voltage Overvoltage Protection (FB

OV)

This family features a FEEDBACK pin that is connected directly

to the output voltage resistor divider network to permit fast

feedback information to the controller for fast load transient

response.

The COMPENSATION pin which is also connected to the

voltage divider network includes a resistor to isolate the slow

feedback path and loop compensation network into the

controller for steady-state output voltage regulation.

Comparators on the FEEBACK and COMPENSATION pins are

used to verify that the pins are not open-circuited and that the

main voltage divider voltage at start-up is greater than FB

OFF

and C

OFF in order to complete the start-up fault detect sequence.

After start-up the FB

OFF and COFF thresholds remain enabled.

Similarly to the original HiperPFS, this controller includes internal

OV (FEEDBACK pin overvoltage), COV (COMPENSATION pin

overvoltage) and C

UV (COMPENSATION pin undervoltage)

protection thresholds that are detected through the FEEDBACK

and COMPENSATION pins. Deglitch filters (t

FB(OV) and tC(UV)) are

also used to prevent the controller from falsely triggering this

protection mode.

A FB

OV event in excess of the tFB(OV) delay will terminate the

switch cycle immediately.

The COMPENSATION pin also features an output voltage

undervoltage detection threshold to detect an overload or

open-loop condition (broken feedback). In the event the falling

edge of the voltage on the COMPENSATION pin falls below the

UV threshold, the MOSFET is disabled and the soft-start

start-up sequence is initiated.

The COMPENSATION pin undervoltage protection (C

UV) mode is

disabled during start-up and enabled once the COMPENSATION

pin voltage exceeds approximately 5.8 V. The brown-out

threshold is also reset from I

UV(SS) to IUV- under the same conditions

as activation of the C

UV threshold.

VCC Undervoltage Protection (UVLO)

The BIAS POWER (VCC) pin has an undervoltage lock-out

protection which inhibits the IC from starting unless the applied

VCC voltage is above the VCC+ threshold. The IC initiates a

soft-start once the VCC pin voltage exceeds the VCC+ threshold.

After start-up the IC will continue to operate until the VCC pin

voltage has fallen below VCC- level. The absolute maximum

voltage of the VCC pin is 15 V which must be externally limited

to prevent damage to the IC.

Over-Current Protection

The device includes a cycle-by-cycle over-current-protection

(OCP) mode which protects the device in the event of a

catastrophic fault. The OCP mode in the HiperPFS-2 is input

line dependent as shown in Figure 13. The intention of OCP in

this device is strictly protection of the internal power MOSFET

and is not intended to protect the converter from output

short-circuit or overload fault conditions.

The HiperPFS-2 latches the high input line OCP for a 1/2 line

cycle and updates the OCP status after the expiration of a 5 ms

block-out timer. This feature has particular benefit for hard-start

after an AC line cycle drop where the peak detector may falsely

detect a low input line condition even though the input is at high

input line.

A leading edge blanking circuit inhibits the current limit

comparator for a short time (t

LEB) after the power MOSFET is

turned on. This leading edge blanking time is set so that

current spikes caused by capacitance and rectifier reverse

recovery time will not cause premature termination of the

MOSFET conduction.

Safe Operating Area (SOA) Mode

Since the cycle-by-cycle OCP mechanism described above

does not prevent the possibility of inductor current ‘stair-casing’,

an SOA mode is also featured. Rapid buildup of the device

current can occur in the event of inductor saturation or when

the input and output voltages are equal (no or very short

inductor reset time).

The SOA mode is triggered whenever the device reaches

current limit (I

OCP) and the on-time is less than tSOA.

The SOA mode forces an off-time equal to t

OCP and pulls the

internal error-voltage (V

E) down to approximately 1/2 of its set

value.

Open FEEDBACK Pin Protection

The FEEDBACK pin also features a static current of I

FB that is

continuously sourced out of the pin to protect against a fault

related to an open FEEDBACK pin. The internal current source

introduces a static offset to the output regulation which must be

accounted for in selecting the output feedback regulation

components.

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