PFS7523 datasheet(5/36 Pages) POWERINT

5 / 36 page

Rev. A 06/15

PFS7523-7529/7533-7539

www.power.com

Figure 5. Idealized Converter Waveforms.

This control produces a continuous mode power switch current

waveform that varies both in frequency and peak current value across

a line half-cycle to produce an input current proportional to the input

voltage.

Control Engine

The controller features a low bandwidth, high gain OTA error-amplifi-

er of which its non-inverting terminal is connected to an internal

voltage reference of 3.85 V. The inverting terminal of the error-am-

plifier is available on the external FEEDBACK pin which connects to

the output voltage divider network with a divider ratio of 1:100 to

regulate the output voltage to 385 V nominally. The FEEDBACK pin

connects directly to the divider network for fast transient load

response.

The internally sensed FET switch current is scaled by the input

voltage peak detector current sense gain (M

ON) then integrated and

compared with the error-amplifier signal (V

E) to determine the cycle

on-time. Internally the difference between the input and output

voltage is derived and the resultant is scaled, integrated, and

compared to a voltage reference (V

OFF) to determine the cycle

off-time. Careful selection of the internal scaling factors produces

input current waveforms with very low distortion and high power

factor.

Line Feed-Forward Scaling Factor (M

ON) and PF Enhancer

The VOLTAGE MONITOR (V) pin voltage is sampled and converted by

a Δ-Σ ADC to a quantized digital value. A digital line cycle peak detec-

tor, with dynamic time constants and multi-cycle filtering, derives and

smooths the peak of the input line voltage. This peak is used

internally to scale the gain of the current sense signal through the

ON variable. This contribution is required to reduce the dynamic

range of the control feedback signal as well as flatten the loop gain

over the operating input line range. The line-sense feed-forward gain

adjustment is proportional to the square of the peak rectified AC line

voltage and is adjusted as a function of the VOLTAGE MONITOR pin

voltage.

At high-line and light load, the feed-forward M

ON variable is dynami-

cally adjusted throughout the line cycle in order to compensate for

the line current distortion through the EMI filter and full bridge

network, thereby improving power factor.

The line-sense feed-forward gain is also important in providing a

switch power limit over the input line range.

This characteristic is optimized to maintain a relatively constant

internal error-voltage level at full load from an input line of 90 to

230 VAC.

Beyond the specified peak power rating of the device, the internal

power limit feature will regulate the output voltage below the set

regulation threshold as a function of output overload to maintain a

constant output power. Figure 6 illustrates the typical regulation

characteristic as a function of load.

Below the brown-in threshold (V

BR+) the power limit is reduced when

the device is operated in the ‘Full’ power mode as shown in Figure 7.

As the input line voltage is reduced toward the brown-out threshold

BR-) and if the load exceeds the power limit derating, the boost

output voltage will drop out of regulation in accordance with Figure 6.

The rated peak power shown in Table 1 is not derated for voltages

below the brown-in threshold when the device is operated in the

‘Efficiency’ mode.

Start-Up with Pin-to-Pin Short-Circuit Protection

At start-up, the engine performs a sequence of operational checks

and pin short/open evaluations, as illustrated in Figure 8, prior to the

commencement of switching. When the input voltage peak is above

brown-in, the engine enables switching.

The OTA error amplifier provides a non-linear amplifier (NLA)

mechanism to overcome the inherently slow feedback loop response

when the sensed output voltage on the FEEDBACK pin is outside its

regulation window. This allows the error amplifier function to limit

the maximum overshoot and undershoot during load transient events.

To reduce switch and output diode current stress at start-up, the

HiperPFS-3 calculates off-time based upon output voltage (V

OUT) during

start-up, resulting in a relatively soft controlled start-up.

Once the applied VCC is above the VCC

UVLO+ threshold, and the output

of the on-chip V

REF regulator is above REFUV+, the value of the

REFERENCE pin capacitor is detected and the full or efficiency power

mode is latched. The pin open/short tests are performed, and if the

FEEDBACK pin voltage is valid the over-temperature OTP is checked

to be false. Once the preceding checks are satisfied the input voltage

is monitored via the VOLTAGE MONITOR pin until it exceeds the V

BR+

threshold [but the peak detector is not saturated]. It is at this point

that switching is enabled.

Timing Supervisor and Operating Frequency Range

Since the controller is expected to operate with a variable switching

frequency over the line frequency half-cycle, typically spanning a

range of 22 – 123 kHz when operating in CCM, the controller also

features a timing supervisor function which monitors and limits the

maximum switch on-time and off-time as well as ensures a minimum

cycle on-time. Figure 9(a) shows the typical half-line frequency

profile of the device switching frequency as a function of input

voltage at peak load conditions. Figure 9(b) shows for a given line

condition of 115 VAC, the effect of EcoSmart™ on the switching

frequency as a function of load. The switching frequency is not a

function of boost choke inductance in CCM (continuous conduction

mode) operation.

IS dt

VOFF

(VOUT-VIN)dt

Latch

RESET

Latch

SET

Gate

Drive (Q)

Maximum

ON-time

Minimum

OFF-time

Timing

Supervisor

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