Rev. A 06/15

7

PFS7523-7529/7533-7539

www.power.com

Figure 9. (a) Frequency Variation over Line Half-Cycle as a Function of Input Voltage (b) Frequency Variation over Line Half-Cycle as a Function of Load.

Note: Frequency Profiles Shown were Analytically Derived and Reflect CCM Operation Across the Entire Line Cycle.

0

45

90

135

180

130

120

230 VAC

180 VAC

135 VAC

90 VAC

Peak Load

115 VAC

100

110

90

80

70

60

50

40

30

20

10

0

Line Conduction Angle (°)

0

45

90

135

180

130

120

110

100

90

80

70

60

50

40

30

20

10

0

Line Conduction Angle (°)

100% Peak Load

75% Peak Load

VIN = 115 VAC

25% Peak Load

50% Peak Load

Expected Frequency

Range at Peak

Rated Load

100% Peak Loaddddddddddd

75% Pk Ld

75% Peak Load

VIN = 115 VAC

25% Peak Load

50% Peak Load

a

50% Peak Load

Expected Frequency

Range at Peak

Rated Load

Figure 10. EcoSmart Frequency Slide V

OFF vs. VE and VOFF(MAX) vs. Input Voltage.

EcoSmart

The HiperPFS-3 includes an EcoSmart function wherein the internal

error signal (V

E) is used to detect the converter output power. Since

the internal error-signal is related to the output power, this signal

level is used to set the average switching frequency as a function of

output power.

As shown in Figure 10, the off-time integrator control reference (V

OFF)

is controlled with respect to the internal error-voltage level (output

power) to allow the converter to maintain output voltage regulation

and relatively flat conversion efficiency from 20% to 100% of rated

load, which is essential to meet many efficiency directives. The

degree of frequency slide is also controlled as a function of input line

voltage. The lower V

OFF slope as a function of input voltage reduces

the average frequency extremes for high input line operation.

Burst-Mode for No-Load Power Consumption Reduction

Under no-load conditions the HiperPFS-3 engine is architected to

enter a burst mode which gates the power switch on and off between

fixed error voltage levels. This ensures low power consumption by

VA

VIN < 140 VAC

4.0 V

(Full Power)

VIN > 170 VAC

4 V 5.2 V

140 VAC

170 VAC

VA

VB

VB

VE

VIN

PI-7228-061615

switching in bursts in order to maintain regulation when leakage

currents constitute the majority of the load. Higher output voltage

ripple at light load is an artifact of efficient burst mode operation.

Power Good Signal (PG)

The HiperPFS-3 features a ‘power good’ (PG) circuit which comprises

an internal comparator that turns ‘on’ an open-drain switch during

start-up when the sensed output voltage on the FEEDBACK pin rises

to ~95% (V

PG+) of the set output voltage threshold. During start-up,

prior to the output voltage reaching V

PG+, the PG signal is in a

high-impedance state (internal switch is in ‘off’ state).

The power good signal transitions from ‘on’ to ‘off’ state when the

sensed output voltage on the FEEDBACK pin falls to a user selected

threshold, programmed with a resistor on the POWER GOOD

THRESHOLD (PGT) pin. The POWER GOOD THRESHOLD pin sources a

fixed current I

PGT. This current combined with the power good thresh-

old resistor sets the threshold when the power good signal transitions

from the ‘on’ state to the high-impedance ‘off’ state as the PFC

output falls out of regulation.