PFS7525L datasheet(9/36 Pages) POWERINT

9 / 36 page

Rev. A 06/15

PFS7523-7529/7533-7539

www.power.com

perform an auto-restart, including FMEA pin fault checks and other

start-up qualifications prior to checking for the line voltage being

above the brown-in voltage by virtue of the VOLTAGE MONITOR pin

being above V

BR+.

After a brown-in event, until after the t

STARTUP timer has expired, the line

voltage brown-out threshold is reduced to V

BR-NTC and the brown-out

timer is extended to t

BRWN_OUT_NTC to allow for the detected drop in line

voltage due to an in-rush limiting negative temperature coefficient

(NTC) thermistor in series with the input line.

If the t

BRWN_OUT_NTC debounce timer is triggered by the sensed line

voltage dropping below the V

BR-NTC threshold but the line voltage

recovers to above the V

BR-NTC threshold before the tBRWN_OUT_NTC expires,

then the t

STARTUP timer will be re-started. If the line does not recover

above the V

BR-NTC threshold before the tBRWN_OUT_NTC debounce timer

expires a shutdown will occur.

After the t

STARTUP timer has expired, if the VOLTAGE MONITOR pin

voltage is qualified above V

BR-NTC, the brown-out debounce timer will

switch to normal period (t

BRWN_OUT) and the brown-out threshold will

switch to V

BR-. If the VOLTAGE MONITOR pin voltage is not qualified

above V

BR- after the subsequent tBRWN_OUT timer has expired then a

brown-out shutdown will occur.

HiperPFS-3 incorporates input waveform discrimination to determine

if the line signal peak-to-average ratio is more representative of a

sinewave or a high duty cycle square wave. The brown-out threshold

is reduced to V

BR_SQ when a high duty cycle (UPS) square wave is

detected.

VCC Undervoltage Protection (UVLO)

The BIAS POWER (VCC) pin has an undervoltage lock-out protection

which inhibits the IC from starting unless the applied VCC voltage is

above the VCC

UVLO+ threshold. The IC initiates a start-up once the

BIAS POWER pin voltage exceeds the VCC

UVLO+ threshold. After

start-up the IC will continue to operate until the BIAS POWER pin

voltage has fallen below the VCC

UVLO- level. The absolute maximum

voltage of the BIAS POWER pin is 17.5 V which must be externally

limited to prevent long term damage to the IC.

Line Dependent Over Current Protection (OCP) limit

The device includes a cycle-by-cycle over-current protection mech-

anism which protects the device in the event of a fault. The intent of

OCP protection in this device is protection of the internal power

MOSFET and is not specifically intended to protect the converter from

output short-circuit or overload fault conditions.

For universal line input parts, the OCP limit is set as a function of the

input line voltage, one setting for low-line voltages and another

setting for high-line voltages. This helps to bound power limit into

short-circuits as well as helps to minimize the stress on the switch

due to current overloads at higher input line conditions. Figure 12

illustrates the hysteretic adjustment of the OCP levels as a function

of VOLTAGE MONITOR pin line-sensing. This equates to selecting the

low-line OCP (the greater of the two settings) when the peak of the

input line voltage drops below 140 VAC for 3 consecutive half-cycles

and selecting the high-line OCP level (the lesser of the two settings)

when the input line voltage rises above 170 VAC for 1 half-cycle,

(except in follower mode, as described in the subsequent sections).

The HiperPFS-3 utilizes a high input line OCP after detecting the

VOLTAGE MONITOR pin above the high-line threshold, V

HIGH+. The

controller reverts back to low-line OCP (as well as low-line frequency

slide) only after 3 consecutive half-line cycle peak values that are

below the low-line threshold V

HIGH-. In the event of a line drop-out,

the controller may revert from high-line to low-line parameters if the

drop-out exceeds 37 ms (nominal). High-line only input parts use a

single fixed OCP threshold.

A follower-mode feature updates the controller to high-line status

rapidly, as soon as the input voltage exceeds V

HIGH+. This feature has

particular benefit for high-line hard-start conditions after a long AC

line drop-out where the peak detector may initially indicate a low

input line condition.

A leading edge blanking circuit inhibits the current limit comparator

for a short time (t

LEB) after the power MOSFET is turned on. This

leading edge blanking time is set so that switch current spikes caused

by drain capacitance and rectifier reverse recovery time will not cause

premature termination of the MOSFET conduction period.

Safe Operating Area (SOA) Mode

Since the cycle-by-cycle OCP mechanism described above does not

prevent the possibility of inductor current ‘stair-casing’, an SOA mode

is also featured. Rapid build-up of the switch current can occur in the

event of inductor saturation or when the input and output voltage

differential is small combined with too little inductor reset time.

The SOA mode is triggered whenever the switch current reaches

current limit (I

OCP) and the on-time is less than tSOA. The SOA mode

forces an off-time equal to t

OFF(SOA) and pulls the internal error-voltage

E) down by 1/2 of its maximum value in order to ensure the switch

remains within its SOA.

Fast Output Voltage Overvoltage Protection (FB

OV)

The HiperPFS-3 features a voltage feedback threshold comparator on

the FEEDBACK pin which detects an output voltage overvoltage

condition to allow rapid response, independent of the COMPENSA-

TION pin response, to prevent hazardous voltage conditions from

occurring. The overvoltage protection is hysteretic – the voltage on

the FEEDBACK pin must drop by 0.1 V (equating to an output voltage

drop of 10 V) before switching is re-started.

FEEDBACK to COMPENSATION Pin Short Detection Safeguard

The PFC controller continuously monitors the FEEDBACK and

COMPENSATION pins to ensure that there are no potential short

conditions between the adjacent FEEDBACK and COMPENSATION

pins, which could result in output overvoltage conditions if not

detected. In the event a potential short is detected, a rapid short

check is performed and a shutdown is executed in the event that a

suspected short is validated.

PI-7255-061615

~170 VAC

~140 VAC

OCP(LL)

OCP(HL)

Figure 12. Line Dependent OCP.

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