STW81102ATR datasheet(24/43 Pages) STMICROELECTRONICS

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I2C bus interface

STW81102

24/43

5.1.7

Multi-byte write mode

The multi-byte write mode can start from any internal address. The master sends the data

bytes and each one is acknowledged. The master terminates the transfer by generating a

STOP condition.

The sub-address decides the starting byte. A multi-byte with sub-address 01H and 2

DATA_IN bytes will change the "B_COUNTER" and "A_COUNTER" registers (01H,02H), so

a multi-byte with sub-address 00H and and 6 DATA_IN bytes will change all the STW81102

registers.

5.1.8

Current byte address read

In the current byte address read mode, following a START condition, the master sends the

device address with the rw bit set to 1 (No sub-address is needed as there is only 1 byte

read register). The STW81102 acknowledges this and outputs the data byte. The master

does not acknowledge the received byte, but terminates the transfer with a STOP condition.

5.2

Timing specification

Figure 23.

Data and clock

Table 10.

Single-byte write mode

1100A2A1A0

ack

sub-address byte

ack

DATA IN

ack

Table 11.

Multi-byte write mode

1100A2A1A0 0 ack

sub-address byte

ack

DATA IN

ack

....

DATA IN

ack

Table 12.

Current Byte Address Read

1100 A2 A1 A0

ack

DATA OUT

No ack

Table 13.

Data and clock

Symbol

Parameter

Minimum time (ns)

Tcs

Data to clock set up time

Tch

Data to clock hold time

Tcwh

Clock pulse width high

Tcwl

Clock pulse width low

cwh

cwl

SDA

SCL

cwh

cwl

SDA

SCL

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